SAN FRANCISCO Aldec Inc., a provider of mixed-language simulation and design tools for ASICs and FPGAs, said Thursday that it would stage private demonstrations of its new generation of system-level design capabilities and features during next month's Design Automation Conference (DAC) in Anaheim, Calif.
Aldec (Henderson, Nev.) said that features of its new platform, scheduled for release during the third quarter, include SystemC and SystemVerilog language support, a high-level C++ testbench engine, a 64-bit simulation engine supporting VHDL, Verilog 2001, EDIF and SystemVerilog, and a complete debugging environment with assertions support.
In addition, Aldec said it would be showing a new system-level mixed analog/digital simulation solution based on the company's VHDL, Verilog and SystemVerilog mixed-language simulation technology and the Turbo Spice simulator. Other new product capabilities would also be demonstrated, the company said.
Customers interested in seeing the private demonstrations can register for them on Aldec's Web site, the company said.