ANAHEIM, Calif. A System Verilog Users' Forum here at the Design Automation Conference on Monday (June 13) gave a rare opportunity for users to speak out through the din of marketing messages that is growing over the battlefield between System Verliog and System C.
Sponsored by Synopsys, which has a strong interest in the outcome of this contest and engineers from Freescale, ARM, and Intel described their experiences with the language.
Ken Albin of Freescale said System Verilog is to a large extent formed by blending parts of the Vera language into Verilog or the value of System Verilog to the verification process. "Our verification methodology needs object-oriented verification features, primarily to foster reuse of verification IP," Albin said. "We also need accurate functional coverage mechanisms. And we are heavily dependent on assertions. In System Verilog, we have a language that allows us to meet all these needs without multiple languages or translations. For example, we have an internal assertion language—CBV—that we have been using. We are moving the CBV assertions attached to our existing IP into System Verilog. As the language features become available in the tools, we adopt them."
ARM's Alan Hunter said design facility where the next-generation Tiger CPU core is being developed agreed. He described an environment in which ARM's enormous legacy instruction set and functional validation suite is used in combination with functional-coverage tools and "pervasive use of assertions." Hunter also described an incremental shift-over from legacy tools. "We still use OVL for simple assertions in legacy blocks, simply because they are in place," he said. "We have been using Synopsys Native Test Bench for functional coverage. We are moving the assertions to System Verilog, and will move over from NTB to System Verilog functional coverage tools when they are avaiable in release 3.1a."
While the first two speakers emphasized the verification side of the language, Matt Maidment of Intel broke with the stereotype and said that Intel is using the system-level design constructs of the new language. "Our experience is that System Verilog is simply a better Verilog," he said. "It leads to a better system design methodology, it captures design intent better, and it puts the methodology on a better evolutionary path. For example, System Verilog allows us to capture the relationships within the data and to encapsulate that knowledge so that it can be shared among the groups working on the design."
Maidment emphasized the evolutionary nature of System Verilog. "With the kinds of pressures that our designs are under today, we don't have the option of making a drastic change in methodology," he declared. "We have to change by evolution, and that is what System Verilog is allowing us to do. But even with incremental change there is a challenge—to use the new constructs effectively without losing our insight into the factors that bring about design convergence."