KYOTO, Japan Circuits will see further performance boosts at the 45-nm node from enhanced strain engineering, and by leveraging different silicon surface orientations, researchers from IBM Corp. said here Tuesday (June 14) on the opening day of the 2005 Symposium on VLSI Technology.
David Fried, a logic device design manager based at IBM's Hopewell Junction, N.Y., development center, said IBM used selective silicon epitaxial growth to create PFETs in bulk silicon with a 110 surface orientation. The NFET transistors were laid out on silicon-on-insulator (SOI) with a 100 surface orientation. Both transistors were stressed nitride layers, the NFET with a tensile strain and the PFET with a compressive strain.
The result was a 30 percent on-current boost for the PFET, and NFET performance that was the same as if the wafer was a conventional SOI wafer. IBM calls the approach HOT, for hybrid orientation technology.
"We are absolutely looking at HOT as a serious contender for use at the 45-nm node. But it is very product sensitive," Fried said. For microprocessors that could afford the additional process complexity, the approach might make sense in terms of the cost-performance benefits, he added.
Meanwhile, Toshiba Corp. unveiled an embedded DRAM technology for the 45-nm node that delivers 6-GB/s bandwidth. For chips such as the Playstation graphics engine that require high bandwidths and low power consumption, the embedded DRAM technology could provide a performance advantage at a relatively modest increase in process complexity.
Toshiba used aluminum oxide as the capacitor dielectric, with little leakage current and good temperature stability. A low temperature process, using a flash anneal technique, was used to create the embedded DRAM array alongside the logic circuits, said Toshiba engineer T. Sanuki.
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) used immersion lithography to create a test SRAM array featuring 20-nm gate lengths, according to engineer Fu-liang Yang. The array represents one of the first reported uses of immersion 193-nm lithography on an SOI process, with a 20-nm silicon body thickness. The TSMC work created SRAM cells with a pitch (line and space) of 90 nm, which Yang said is among the smallest pitch reported to date.
The 2005 symposium is the 25th meeting of the conference, which alternates between Kyoto and Honolulu.