Silicon on insulator (SOI) semiconductor fabrication offers a great opportunity to improve radiation-hardened (rad-hard) ASICs when combined with a hardened library and very-deep-submicron (VDSM) design flow and infrastructure. Such a capability can allow high-performance ASICs with gate counts exceeding 10 million gates to be protected against radiation effects, with minimal effort on the part of ASIC designers.
Historically, rad-hard applications have not been able to step up to the latest technologies and silicon manufacturing processes. High gate counts and associated high clock speeds represent a dramatic change for rad-hard electronics.
Advancements in rad-hard ASIC technology are required because the latest non-hardened commercial ICs still exhibit errors and reliability problems when exposed to radiation environments. Radiation phenomena such as single event effects occur in space applications, in aircraft at high altitudes, and even in terrestrial environments.
Specialized SOI fabrication and appropriate libraries and tools provide embedded protection against these radiation hazards. While higher-level techniques such as triple/majority voting and error-correction codes may be necessary for some applications, embedded protections built into the silicon process and design flow provide a highly effective foundation for radiation tolerance or radiation hardening.
For applications ranging from military/aerospace to implanted medical electronics, the hardening techniques address the reliability, signal integrity, parameter shifts and single-event upsets associated with various types of radiation (Table 1).
Table 1 Radiation sources, impact, and mitigation
Radiation hardness can be built into the IC at several levels with little effort on the part of designer. The first level is the silicon-on-insulator (SOI) process that provides safeguards against many radiation effects and can be modified to handle others.
The second level of hardening is within the cell libraries, where radiation protection is enhanced by specific design practices and physical design. The third level is related to ASIC design implementation and is supported by the ASIC design process and software tools.
Silicon on insulator advantages
SOI offers many inherent advantages by using a thin film of silicon on top of an insulator. While bulk CMOS relies on junction isolation between devices, SOI uses dielectric isolation to surround the entire device sides and bottom. SOI has no wells into the substrate and therefore has no latchup or leakage paths.
These advantages simplify fabrication steps, improve density and reduce parasitic capacitance. The result is up to 30 percent lower power consumption, 20 percent higher performance and 15 percent higher density than traditional bulk CMOS at the same feature size.
While this article cannot describe every type of radiation effect, it is useful to consider some of the more critical effects as examples of SOI's benefits. For instance, SOI inherently eliminates latchup, which can occur in CMOS devices due to a parasitic condition in which at least one PNP and at least one NPN transistor act like a silicon controlled rectifier (SCR) if turned on in a prompt dose or single event upset (SEU) event.
This parasitic PNPN structure creates a low-impedance path between the power rails and can permanently damage the device. Because the wells in an SOI device are completely oxide isolated, the parasitic SCR effect cannot occur.
In contrast to commercial SOI, radiation-sensitive devices require hardening of the buried oxide and trench isolation. Without this hardening, charge induced by gamma rays can get trapped over time in the buried oxide, then recombine next to the oxide/silicon interface and change a device's threshold voltage. The SOI structure can be built to provide places where charge can recombine away from the oxide/silicon interface.