LONDON ARM Holdings plc said Wednesday (July 13) it demonstrated the first ARM11 MPCore multiprocessor, with a power consumption of 600-milliwatts while delivering 1440 dhrystone MIPS of performance, to a set of ARM partners at its Cambridge offices in May.
The test chip, based on the ARMv6 instruction set architecture, comprises four processors running with cache coherence and was made by NEC using a generic 130-nm manufacturing process with no optimizations for performance or power, the company said.
The test chip has been operated at clock frequencies of up to 300-MHz, according to John Goodacre, multiprocessing program manager at ARM, and importantly had come back from NEC "right-first-time'. "The chip was intended to allow us to test the functionality of the multiprocessing design and caches. As such it was made with a conservative choice of process and libraries. Despite that we have created the highest throughput single-chip ARM processor."
Goodacre, speaking to EE Times immediately before presenting at the MPSOC conference in France, said that ARM's licensees would be able to apply the synthesizable design to higher-performing 130-nanometer processes, optimized libraries and achieve and could expect to achieve 350-Hz to 550-MHz clock frequency performance that it is typical of commercial ARM11 uniprocessors.
One year ago ARM said the MPCore could be configured to contain between one and four processors and would deliver up to 2600 Dhrystone MIPS of performance
(see May 17, 2004, story).
Goodacre said the MPcore was exactly on target to allow commercial implementations to achieve that, but give no indications as to when licensees were likely to deploy ARM multiprocessors.
The only known licensees of the MPcore are NEC, ARM's lead partner, and NVidia Corp.
The demonstration was conducted with existing applications developed for non-multiprocessing system technology, ARM said, and included automatic balancing of application loads among processors with an overall reduction of consumed energy.
The ARM11 MPCore processor test chip is "right-first-time" and is the result of an ongoing collaboration between ARM and NEC to co-develop a next-generation multiprocessor core based on symmetric multiprocessing, the company said. It is supported by the OpenMP compiler technology from KTH Royal Institute of Technology of Sweden, and implements 'Adaptive Shutdown' and Intelligent Energy Manager technology to reduce power consumption by up to 85 percent. NEC Electronics intends to use the MPcore across the consumer electronics, automotive and mobile markets.