SAN FRANCISCO Agilent Technologies unveiled its approach to production memory test systems at the Semicon West show.
Aimed at the problems posed by the skyrocketing use of multichip packages (MCPs), Agilent's system promises single-insertion, highly parallel full-speed testing of packaged MCPs.
Gayn Erickson, Agilent's vice president of memory test, said MCPs have become a big part of the memory business much more quickly than anyone expected. "Over 50 percent of NOR flash parts this year will go into MCPs," he said. "I know of no new cellular handset design now underway that is not using MCPs."
Not only are the stacked packages ubiquitous, but they are becoming more complex, Erickson said. He cited one Samsung phone with an eight-die stack. Further, the variety of memory types in the stack is growing. "It is increasingly common to find all four major memory types DRAM, SRAM, NOR flash and NAND flash all in the same stack, and often sharing some I/O pins," he said.
This is creating a huge problem for memory test vendors. One package must be subjected to several entirely different kinds of memory test sequences. Pin counts are well beyond anything envisioned for memory testers, cutting down on the number of packages that can be tested in parallel. The result is lower throughput, directly increasing test cost and multiple insertions. All directly increase yield loss because of the fragile, temperature-sensitive contact balls on packages.
Adding to the burden, Erickson said, memory companies are offering their MCP capabilities as a virtual mix-and-match business. Customers can select the memory dice they want from a menu on a vendor Web site, place an order and the MCP is delivered by an assembly contractor. The problem is that the MCP arrives on the test floor with no procedures for combining tests for various dice inside, and no fixturing. It's a prescription for trouble, Erickson said.
Agilent said the solution is a new test system, the V5500. Key system components are more than 16,000 physical pins and a proprietary switching matrix chip that completes the connections between the roughly 4,000 physical I/Os on the tester and the 16,384 pins that can be software-defined and quickly altered.
The matrix chip allows a tester signal line to be connected to up to four pins in parallel, addressing the problem of parallel test. But the prime value of the matrix is flexibility: signal-to-pin mapping can be completely revised in about 100 microseconds. This allows all of the pin mappings and test programs necessary for the different kinds of memory dice in an MCP to be applied without reinserting the package. Since all of the tester pins are full I/Os, designers can select the pinout for the package.
The system can also deliver high levels of parallel test for discreet flash memory devices, making it attractive for a mix of discrete and MCP tests.