SAN FRANCISCO The development of robust process models that can easily be integrated into the design flow is the single most important step toward helping the semiconductor industry overcome the challenges associated with design for manufacturing (DFM), concluded a panel of industry executives at the Semicon West tradeshow here Wednesday (July 13).
"The myth is that there is some magic marketing concept called DFM that you can just turn on," said Mark Mason, manager of reticle enhancement technology at Texas Instruments. "It's really an entire culture that needs to be implemented."
Mason warned that "business as usual" will not work at the 45-nanometer technology node and that big changes were needed to help the industry continue technology shrinks.
"DFM is no longer one of those nice things to have to improve yield," Mason said. "DFM is going to be an enabler at the 45-nanometer node. If you don't have it, you will not yield silicon."
Panelists agreed that communication and close collaboration are absolutely essential elements for overcoming DFM challenges.
"DFM is a contact sport," said Michael Smayling, chief technology officer of Applied Materials' Maydan Technology Center. "You've got to be communicating closely, effectively and systematically."
Christopher Progler, vice president and chief technology officer at Photronics Inc., said real partnerships between photomask suppliers, EDA vendors and equipment providers must occur to drive next-generation DFM technology.
Progler said one of the challenges posed by DFM is that it is difficult to define. He argued that a number of things, including optical proximity correction (OPC), may be considered DFM by some and not by others. Well-defined DFM problems can yield high-impact solutions, he said.
Mason said the root of many DFM problems is that, even at the 90-nm node, the industry is still using 193-nm photolithography, which he characterized as "too large a brush." He noted that at the 45-nm node logic gates would be around 30 nm, but the industry would still be using 193-nm lithography.
Dipu Pramanik, group director of research and development for Synopsys Inc.'s Silicon Engineering group, said to overcome DFM challenges, the EDA industry needs to create tools that capture physics more completely and a greater dialog between process development and design during the early stages of technology development is needed. The most important thing, Pramanik added, is that the industry needs to create a framework to share critical information between manufacturing and design regarding process variability without compromising intellectual property (IP) on both sides.
Pramanik said the industry needs to develop a methodology for encrypting yield models that would protect the process IP of foundries.
Rob Shaddock, chief technology officer of Motorola's Mobile Devices business, said better simulation tools in order to "find bugs before the production ramp."
Pramanik noted that the industry is clamoring for DFM technology and that Synopsys and other EDA suppliers have no choice but to invest in product development.
"People want DFM," Pramanik said. "If we don't make investments in it, people are going to stop buying Synopsys tools."
Photronics Progler said the semiconductor industry would spend the money to overcome DFM, noting that the industry spends as much as $500 million to develop next-generation lithography tools that will enable future shrinks.
"The industry is willing to spend big money to solve problems when it needs to," Progler said.