MARGAUX, France Viable system-on-chip (SoC) business models require an integration of design and manufacturing, along with new types of businesses and alliances, according to several speakers at the Multi-Processor SoC (MPSoC) forum here Friday.
Raul Camposano, CTO of Synopsys, discussed the need to move to "yield-centric" design for manufacturing (DFM). Youn-Long Steve Lin, co-founder and CTO of Global Unichip Corp., described setting up a design services firm associated with TSMC. And Philippe Magarshack, group vice president of front-end technology and manufacturing at STMicroelectronics, showed how the Crolles2 alliance is bringing up new process nodes.
"Design used to be isolated from fabs and lithography, and now that barrier is breaking down," said Camposano. A few quick numbers show why. Between 130 and 90 nanometers, he said, design costs nearly doubled and mask costs more than doubled. Manufacturing costs came down, but are still 74 percent of the total.
Camposano noted that optical proximity correction (OPC) has helped spawn a "whole new industry" that helps ensure "litho-centric DFM." But now, he said, there's a need for "yield-centric DFM" that looks at process variations as well as lithography. EDA vendors can help, he said, with yield-aware physical synthesis, layout practices such as wire spreading and redundant via insertion, and critical area estimation.
Camposano said that reticle enhancement technology (RET), which includes OPC, is the fastest growing segment in EDA, and that Synopsys is aware of over 30 startups in the DFM area.
As the design community looks towards manufacturing, the manufacturing community is looking towards design. At least that's the case in Taiwan, Lin said, where it's now recognized that there's a need to have an internal IC design capability.
Lin, a professor at National Tsing Hua university in Taiwan, was a founder of Global Unichip Corp., which seeks to provide an "SoC design foundry." The idea, he said, is that "a systems house comes to us with a specification and we handle everything, including packaging and testing, and deliver a finished chip to customers." One goal, he said, is to increase TSMC's business by ten percent.
But the company has run into some challenges. Among them are inconsistent simulator versions between customers and Global Unichip, the lack of good SoC testing solutions, and problems with third-party intellectual property (IP). "Most IP providers are very weak in test support," Lin noted.
Magarshack noted that the cost to bring up a new process node rose to $1 billion dollars at 90 nm. "Fewer and fewer semiconductor companies can afford to put a billion dollars into R&D before generating revenue from it," he said. This reality caused ST to join with two competitors, Freescale Semiconductor and Philips Semiconductors, to create the Crolles2 alliance in 2002.
Today, that alliance has grown to encompass 750 engineers, a $1 billion joint investment, and partnerships with advanced R&D labs. The partnership is working not only on process development, but also libraries. Magarshack described the Libraries and IP Partnership (LIPP), which is now ramping up on 65 nm design kits and libraries though multiple sites in the U.S., Europe, and India.
"Some time ago, there was a much longer market window, but now you have to be first time right," said Magarshack. "This is why we need to share."