Pity the poor MOSFET. Once the star of microelectronics the ideal blend of elegant simplicity and unlimited scalability that made the global industry possible the planar metal-oxide-semiconductor field-effect transistor appears to be approaching the end of its useful life. It leaks where it shouldn't. It's plugged up where it should be open. And repeated attempts to keep it functioning have left the vital parts dangerously thin.
But if the planar MOSFET is in trouble, what comes next? Some experts say there really is no replacement that new materials, more advanced fabrication techniques, maybe a new substrate will keep the little guy going well into the next decade. Others believe only a move to a radically different, three-dimensional structure can keep device scaling on track much beyond the 45-nanometer chip-manufacturing node.
"There are several problems with the planar MOSFET today," said Shang-yi Chiang, senior vice president of R&D at Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan). "The biggest problem, in my view, is the short-channel effect. The second critical problem is thinner gate oxide. Both cause increasing leakage , but from different mechanisms."
The short-channel problem is a source of subthreshold leakage between the source and drain. When any MOSFET is turned off, the active region of the channel directly under the gate becomes depleted of carriers and ceases to conduct current. But as you get farther away from the gate, the field weakens and the clampoff effect diminishes. As you make transistors smaller with a shorter effective gate length the area under the clamped-off region becomes short enough to be a conducting path.
To exert a stronger electric field in the channel both to speed switching and reduce leakage current designers have made the gate oxide thinner in each succeeding generation. In the 65-nm process generation, the oxide on high-performance transistors is thinned to 12 angstroms so thin that the tunneling current between the gate and the channel has become significant. Any more thinning, and the transistor would be nearly useless.
"According to our models, to build a transistor at the 32-nm node would require a channel length of 18 nm and a 7-angstrom oxide," Chiang observed. "I believe this would not work with the planar structure we are using today."
"Gate current related to the dielectric in the gate stack will be the first challenge," agreed Jim Huang, senior department manager at Taiwanese foundry United Microelectronics Corp. "Controlling short-channel effect will also be a challenge."
"We have a lot of knobs to turn to tweak the performance of the planar MOSFET," said Ghavam Shahidi, director of silicon technology at IBM Research. "The problem is that they are all hitting their limits. In addition, we are seeing parasitics creep up as we decrease dimensions."
The parasitics issue is critical, in the view of some experts. The series resistance of the transistor keeps increasing, as does contact resistance. As the elements in the transistor move closer together, coupling resistance and capacitance between the pieces is becoming a problem.
"Miller capacitance between the drain contact and the gate electrode is becoming an issue in performance," said Serge Biesemans, a research director at the Interuniversity Microelectronics Center (IMEC; Leuven, Belgium). "By 45 nm, contact-to-poly [-silicon gate] capacitance is going to hit very hard. And beyond 65 nm, all the knobs are already turned to maximum."
Can we squeak by?
In the past, the response of the semiconductor industry to such challenges has always been to tackle the problems one by one, find solutions that will work for a generation or two and push forward. And this is happening once again.
The attack on subthreshold leakage current has begun by trying to make the channel region as shallow as possible. This is done by keeping the channel implant and hence, the junction between the channel and the bulk silicon below it very shallow, in what is called an ultrashallow-junction technique. But an ultrashallow implant, if heated, will tend to diffuse downward. So the technique imposes severe thermal restrictions on subsequent processing steps.
High-k dielectric materials were supposed to ride to the rescue about now, improving the electric-field strength in the channel and thus reducing leakage for a given dielectric thickness. The plan was to combine high-k with a metal gate, which would give a superior work function and eliminate the depletion region that forms at the bottom of the polysilicon gate electrode. (Work function describes the structure of the energy bands at the interface between materials; since it determines how carriers and electric fields will behave in the area, it is crucial to how well the transistor will work.) The depletion region increases the effective dielectric thickness and thus decreases the effectiveness of the gate.
But both high-k and metal-gate technologies have proved far from easy to integrate. "This path calls for new, hostile materials to be introduced into the process flow, each with its own fundamental problems," said Greg Higashi, chief technology officer in the front-end process group at Applied Materials Inc. (Santa Clara, Calif.). The integration problems have delayed the materials' arrival.
"I don't think high-k and metal-gate technologies will be ready for 45 nm," TSMC's Chiang said. "Maybe, in some transistors, at 32 nm."
If there's not much to be done to reduce subthreshold leakage, the next best thing is to increase drive current by improving carrier mobility in the channel. This has been the success story of strain engineering.
"We introduced strain on the channel at 90 nm and took it to the next increment at 65 nm," said Ben McKee, vice president in charge of the 45-nm development team at Texas Instruments Inc. (Dallas). "The assumption is that we will increase it again at 45. We keep on making progress in the materials that induce strain in the silicon lattice. But the question is how much strain we can induce without risking fracture. I think we will see the fracture point on the horizon already at 45 nm."
IBM's Shahidi foresees a similar scenario. "We will see higher-stress liner film, heterogeneous crystal orientation and, perhaps, stressed silicon germanium embedded in bulk silicon. Germanium, and eventually III/V materials, could be a big help."
How far can all this take chip makers? IMEC's Biesemans thinks metal gates and oxynitride films can get the industry to 45 nm. TI's McKee also thinks that at 45 nm, semiconductor manufacturers will still be using relatively conventional structures in combination with metal gates and high-k material. "But we have yet to find a high-k material that has a good integration path and a good work function," he warned. "We may see metal gates introduced by themselves first."
TSMC's Chiang would not be surprised to see fully silicided gates even before metal gates. Others, including Shahidi and Applied Materials' Higashi, think these steps could take chip makers as far as the 32-nm node. But no one sees a clear path to a planar 32-nm transistor.
One point many experts made was that beyond 65 nm, transistors for low power, for high performance and for general use will start to diverge. "The high-speed transistor bumps into the short-channel wall first, but designers will tolerate some leakage there," Chiang said. "The low-power transistor can't tolerate leakage and may be the first application of high-k materials." In short, there is a very real possibility of seeing fundamentally different materials being used on the same die in nets with different timing slack.
For the high-speed transistor, at some point all of the knobs are at their stops and all of the tricks have been played. What then? Two categories of answers emerge: fully depleted silicon-on-insulator (SOI) and multigate structures.
In both cases the idea is the same: Get all of the channel so close to the gate electrode that when the transistor switches off, the whole channel becomes a depletion region, conducting only a tiny current. This, of course, is also the aim of ultrashallow-junction transistors today.
But the proposed techniques take the idea to new heights. In fully depleted SOI, the transistor is fabricated in a silicon film bonded to an insulating substrate. But unlike today's SOI processes, the substrate is so thin that the entire channel becomes depleted in the gate's electric field.
STMicroelectronics proposes a variant on this theme. Called silicon-on-nothing, the process starts with ordinary bulk silicon. A thin implant is driven beneath the regions where transistor channels will later be placed. Through clever techniques, this layer is then removed and replaced either with nothing at all (hence the name) or with an insulator. Then an ordinary MOSFET is built, with an ultrathin body resting on top of the empty space.
Most of the attention on advanced transistors has gone to the oddest-looking of the alternatives: multigate devices. The poster child for these is the FinFET.
In all such devices, the channel, instead of being simply the heavily doped region under the gate, becomes a vertical structure on edge: a bridge through the dielectric material, connecting the source to the drain. Some number of gates usually three enclose this little fin of doped silicon in between the source and drain, forming the channel. "Think of the FinFET as two ultrathin-bodied FETs joined back-to-back," Chiang said. "There's a gate on each side, and together they control the channel completely."
In many FinFETs, the gate is actually a continuous piece of metal that wraps around the top and both sides of the finlike channel. But Chiang pointed out that since the top portion of the gate in such a device would be acting on a different crystal orientation of the channel than the side gates, its interface state would be different. Hence, it would behave differently from the sidewall gates. And the tiny transistors formed in the corners of the fin would be problematic as well.
In schematic form, the FinFET looks like a nice, robust and reasonable device. But the reality is quite different. To control the channel adequately, the width of the fin can't be more than half the effective channel length, according to Chiang. Where the effective channel length is 18 nm, that means a long, tall fin only 9 nm wide. Problems in fabricating and protecting such structures are obvious.
Not so obvious but equally serious are problems with variations. "Line edge roughness is a major cause of variability and will have to be suppressed," warned Tohru Furuyama, general manager of the system-on-chip research and development center at Toshiba Corp.
TSMC's Chiang was also skeptical: "It's hard to imagine controlling strain in such a free-standing structure as the fin. But the device will have to have substantial channel strain in order to have adequate performance."
As enthusiasm over the FinFET has waned, other suggestions have crowded in. Intel Corp. has presented papers on what it calls a trigate device: similar to a FinFET, but with a low, wide bar instead of a tall, narrow fin. Toshiba and others have discussed an Omega-FET a channel with a rounded vertical cross-section, like the Greek uppercase omega, instead of the rectangular fin. Others are looking at ways to include two gates in a planar structure.
Certainly, everyone will stay with conventional planar structures through 45 or maybe 32 nm. Several experts said the first use of nonplanar devices would be in dense memory structures. But will the high-speed logic transistor at some point be nonplanar? Most experts would not give an unequivocal yes.