It was probably no surprise to anyone when the idea of reuse first started to appear in the development of chips. At first the industry turned to salvaging, or the reuse of blocks that were never intended to be reused. Later the ability to buy pre-designed blocks of functionality from third parties, which could be hooked together by the system designer, enabled huge chips to be put together in a fairly short amount of time.
New tools being introduced today make that even easier and quicker to manage. The Virtual Socket Interface Alliance (VSIA) was formed to help the industry tackle many of the technical, managerial and legal issues surrounding the silicon intellectual property (IP) industry, and its success has enabled the industry to grow faster than it would have been able to if there had been no unification in these areas.
But the IP market still has a bad name. Some still question the value of reuse, but in most cases the target of this criticism is wrongly placed. Designers creating IP blocks are not second rate engineers using bad methodologies or sloppy verification techniques. In fact, in some cases, they are using the most advanced and thorough techniques available. So what is the fundamental problem?
Design is getting more efficient
Industry statistics currently show that approximately 70% of the design time is being spent in verification. Whether the actual number is right or wrong is not clear, but it is clear that verification is taking a larger portion of the total development time and is growing rapidly.
This should come as no surprise. Many tools have been developed which increase the productivity of the design process. Synthesis and reuse, notwithstanding the issues raised here, are the two biggest contributors. Even with an increase in complexity, the time spent in design has been declining. As IP blocks get larger, that total time will continue to decline.
But the same cannot be said for the verification side. While recently there have been some productivity improvements with the introduction of pseudo random generation and coverage based techniques, the productivity increase has been much smaller than for design. So even if design and verification efforts started off equal, the balance will continue to shift to a greater percentage of the available time being spent on verification. Something has to happen to stop this and bring both tasks back into balance.
IP needs to be verified
When blocks were salvaged from previous designs and modified for the current design, there was basically no reuse on the verification side. It was unlikely that even if the testbenches for the original block existed or could be found, that they would be reusable for the modified block.
In the early days of the third party IP industry, changes and customizations were not uncommon. This again meant that verification of the blocks had to be performed from scratch. As the industry has matured, changes are now the exception rather than rule, but there is a still a lack of trust between the vendor and user when it comes to knowing if the blocks will work correctly.
These problems stem from a multitude of issues, such as the IP provider having to make sure that the block works with a multitude of EDA tool flows, in any number of silicon technologies, in any combination with other blocks, or is being used in ways that were not considered by the original developers. Complete verification with all of these variables may take longer than the viable market window for the IP block. So just when the IP block is becoming stable, nobody wants it any more as it has been replaced by newer, faster, better blocks.