Palo Alto, Calif. Parallel architectures emerged as the locus of attention in chip design at last week's Hot Chips 17 conference here. Hot Chips used to be about bigger and faster processors and ever-higher clock frequencies. But this year, the predominant theme among conference papers was not raw speed, but parallelism finding it, exploiting it with hardware and avoiding the bottlenecks that threaten to undermine those efforts.
The reason for this shift a gradual process over recent years was clear. On the transistor and circuit level, chips aren't going to whiz along much faster than they do now. The conspiracy of increasing parasitics, deteriorating transistors and spiraling power dissipation will make further progress in uniprocessor systems slow and painful. So architects are turning to multiprocessing, in any form they can adapt to their applications. And in one possibly prophetic paper, from IBM Corp.'s Zurich Research Laboratory, they are turning away from instruction-driven processors altogether.
While many issues of legacy architectural thinking, hardware implementation and, especially, programming support tend to obscure it, chip architecture has become a simple battle to preserve and exploit whatever parallelism exists in an algorithm and its data. This new reality is opening a profound gulf between embedded systems, where the algorithms and structure of the data are known in advance, and fully programmable systems, in which they are not.
In the embedded world, the first question is whether the parallelism exists in the data, in the algorithms or both. So far, data parallelism has been the most rewarding situation for chip designers. If a transformation can be applied independently to many groups of data, the degree of parallelism is in theory limited only by the amount of data available at one time and the complexity of the transform. You can still run out of transistors.