One of the factors in decreasing chip power consumption, which is key for mobile and battery-operated devices, is improving the design of the transistor. Lost electricity leaking from these transistors, even when they are in their “off” state, is a problem that is a challenge for the entire industry.
With P1265, Intel now has two 65-nm processes: one for high-performance devices and the other for ultra low-power designs. The high-performance, 65-nm process is called P1264 by Intel. Like P1264, which was rolled out back in 2003, (see Nov. 24, 2003 story) the P1265 process is an 8-metal layer technology equipped with copper interconnects, low-k dielectrics, and strained-silicon.
“Test chips made on Intel’s ultra-low power 65-nm process technology have shown transistor leakage reduction roughly 1,000 times from our standard process,” according to the Intel technologist. “This translates into significant power savings for people who will use devices based on this technology.”
The P1265 process is said to have demonstrated leakages of only 0.1-nA/micron, as compared to 100-nA/micron for the high-performance process, according to Intel.
To enable the breakthrough, Intel has modified its 1264 process. These transistor modifications result in reductions in the three major sources of transistor leakage: sub-threshold leakage, junction leakage and gate oxide leakage.
Surprisingly, Intel plans to increase the thickness of the gate oxide to reduce leakage, Bohr said. “Thicker gate oxides could be saying that we’re going backwards,” he said. “You give up something in performance.”
The company also plans to deploy a simple, low-dosage implant step “to increase the sub-threshold voltage of a device,” Bohr said. In the ultra-shallow junction portion of the device, Intel plans to implement a “high-dose implant step followed by an anneal.”