SAN JOSE, Calif. Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) said Wednesday (Oct. 5)its has completed the first run of its 65-nm CyberShuttle prototyping service carrying customer designs.
Designs for five customer chips and test patterns for several third-party IP blocks were included on the multidesign shuttle wafers.
The first shuttle employed two versions of the TSMC 65-nm process: the CLN65LP low-power process which includes low-standard and high-threshold transistors; and the CLN65G general-purpose process.
According to TSMC, individual designs from Altera Corp., Broadcom Corp. and Freescale Semiconductor were included in the shuttle run, along with several IP developers.
TSMC's schedule calls for two more 65-nm shuttle runs before the end of the year, and at least one 65-nm shuttle run every two months during 2006. Bookings are already strong for the future runs, the company said.
In addition, the foundry expects to ship the first production wafers from its CLN65LP process late this year. Production start-up for the CLN65G process is not expected before the fourth quarter of 2006, just after the first shipments from the as-yet-unsampled CLN65HS high-speed process.
A company spokesman said demand for early shuttle runs confirmed TSMC's belief that initial interest in the 65-nm process would come primarily from wired and wireless consumer chip designers. The process, which was developed very conservatively to use nearly all the same materials and procedures as TSMC's 90-nm processes, gives designers a substantially larger transistor budget about twice the standard-cell density of the 90-nm process but without any magic bullets that could drastically reduce power consumption or increase performance.
Thus, the process is perhaps most attractive to customers seeking either smaller die sizes or higher gate counts. Most consumer chip designers would fall in the former category, and Altera would clearly benefit from both smaller dice and larger maximum gate count.