SAN JOSE, Calif. Design for manufacturability (DFM) concerns have slowed the ramp-up of 90 nm wafer volumes and will be even more problematic at 65 nm, said Handel Jones, CEO of International Business Strategies Inc., at the Fabless Semiconductor Association Expo here Thursday (Oct. 6).
Jones moderated a panel on DFM in which he presented IBS' latest research. Jones' presentation, along with the panelist comments that followed, provided a warning and a call to action.
Jones noted that 90 and 130 nm wafers use the same materials, yet the ramp-up times were under a year and a half for 130 nm, and over two years for 90 nm. "So why the delay? Our analysis is that leakage is the major factor impacting low yields," Jones said. This includes both sub-threshold and gate-oxide leakage, he noted.
Leakage, according to Jones, is the primary factor in design-related yield loss. And at 90 and 65 nm, design-related yield loss is more significant than process-related and reticle-related yield loss, according to IBS data. At 65 nm, design-related yield loss alone may reduce yields by as much as 30 percent, Jones said.
Non defect-related yield problems increase as feature sizes reduce (International Business Strategies, Inc.)
Jones also noted that manufacturing and design costs are taking a larger and larger percentage of total revenues. At 90 nm, the manufacturing cost is 60.4 percent of total revenues, while design cost is 11.7 percent. At 65 nm, IBS projects that the manufacturing cost will be 69.4 percent of revenues, and the design cost 16.8 percent. "The cost factors are going in the wrong direction," he said.
Jones also cited a very high level of inefficiency in silicon gate utilization. At 90 nm, he said, a typical ASIC or ASSP uses around 13 million gates, compared to an available gate count of 30 million gates for a 10mm x 10mm die. Gate utilization isn't expected to be much higher at 65 nm, where 100 million gates will be available.