Tokyo Matsushita Electric Industrial Co. Ltd. will make a strategic move from 130-nanometer manufacturing to the 65-nm generation this month as it begins to ship 65-nm chips in volume. In doing so, the company has bypassed the 90-nm generation.
"Matsushita will design all major system-on-chip LSIs on a 65-nm process from now on," said Susumu Koike, Matsushita's senior managing director in charge of technology and president of Matsushita's semiconductor company.
Consumer IC manufacturers like Sony and Toshiba have announced development of 65-nm process technology, but have not begun volume production.
Matsushita completed its 300-mm wafer fab in Uozu City, Japan this month, two months earlier than planned. "I believe we have entered the 65-nm generation earlier than any other company for the volume production of system-on-chip LSIs, especially in low-power-consumption processes," said Koike.
In assessing the 90-nm node, Matsushita decided that "the market outlook was not a lucrative one," said Koike. "If the market is tough, we have to be agile in revising our plans. Our engineers had a hard time making the transition, but that's their job and they did it well. We had completed the development of 90-nm process technology, thus we could jump [more easily] to 65 nm."
Matsushita developed its 65-nm process technology with Renesas Technology Corp. The process uses argon fluoride (ArF) dry lithography combined with Matsushita's proprietary resolution-enhancement technology. The RET technology combines a conventional halftone mask with a special resist that enhances the contrast.
While standard halftone masks can cut up to 100-nm-diameter holes, Matsushita's resolution-enhancement technology enables the cutting of 80-nm-diameter contact holes and is capable of cutting 65-nm holes. The technology is also applicable to ArF immersion lithography, according to Hirofumi Uchida, director of the ULSI process technology development center at Matsushita's semiconductor company. Matsushita already has 21 patents that involve the technology.
Matsushita's 65-nm process uses nickel silicide to accelerate transistor speed, a low-k SiOC film and dual-damascene copper wiring.
DVD chip is first
The first 65-nm LSI device to ship will be a seven-copper-layer CMOS system-on-chip for DVD products. Its transistor gate length is 55 nm and the first layer of copper interconnect has a 180-nm pitch, with a 200-nm pitch for the second layer. These numbers are smaller than the ones on the International Technology Roadmap for Semiconductors 2004, which said the first layer should be 190 nm and the second layer, 240 nm.
The first chip to be produced will be packaged in a 677-pin BGA. A second chip will be shipped early next year. In addition to using the devices in-house, Matsushita plans to sell them commercially.
Although the two devices were not designed on the UniPhier platform, which Matsushita created to integrate hardware and software resources to improve design efficiency, the 65-nm process and the UniPhier platform work in tandem in Matsushita's semiconductor strategy. "Scaling down means better cost performance, higher [device] performance and higher reliability," said Koike.
Matsushita has reduced the chips needed for a system with each process node, from 17 using a 250-nm process in 2000 to one using the 65-nm process by 2006.
Matsushita has invested about $1.1 billion in its Uozo fab to establish an initial monthly capacity of 6,500 wafers. The company expects the fab to reach full operation in 2007 or 2008.
The fab has room to add another 5,500 wafers a month, to increase capacity to 12,000 wafers/month. "We want to expand the capacity to the maximum around 2009, depending on the market situation. At that time, we may use the 65-nm process or a more-advanced-generation process," said Koike.