Austin, Texas Just as giants of the retail world are erecting massive "megastores," so the chip industry is eyeing supersized foundries to build the ICs for the products that wind up on those retailers' shelves.
"Consumer-use [semiconductor] products are driving manufacturers to a new frontier," Mark Liu, vice president of operations at Taiwan Semiconductor Manufacturing Co. Ltd., said at a manufacturing-productivity conference here last week.
Fab 14 is part of that new frontier, Liu said. This "gigafab," located in the southern Taiwan city of Tainan, will cost upward of $10 billion before it is filled out but will deliver wafers at lower costs than smaller fabs.
Intel Corp. and Samsung Electronics already operate gigafabs in Albuquerque, N.M., Ireland and South Korea, said Dan Hutcheson, CEO of market research firm VLSI Research Inc. Fab shells can be built large, and then equipped gradually to meet market demand. TSMC's Fab 12, for example, was started in 1999 and is still being expanded, "accordion-like," Hutcheson said.
The advantage of the gigafab is efficiency. Huge fabs can produce chips as much as 10 percent more cheaply than midsize fabs, said Hutcheson. That's because software costs can be spread out, machines can be bought in larger volumes and fewer bottlenecks develop, he said.
TSMC's Liu defined gigafabs as facilities with monthly capacities of 80,000 to 100,000 wafers, whereas "megafabs" have run rates of 50,000 wafers per month.
With consumer electronics now complementing computing and Internet-based communications as the industry's drivers, chip manufacturers face "a different set of mind," Liu said. "In the consumer era, there is no room for overdesign, and there is little premium for performance. There is strong price elasticity, but often there is no dominant standard." Also, foundries often face steeper production ramps for consumer-use chips, he said.
The 300-mm Tainan fab, which has a clean room space of 20,000 square meters, is being built in phases. TSMC is now planning a third phase that will expand capacity by 20,000 wafers, to 100,000 wafers/month. But the expansion plans depend on market conditions, Liu said in a keynote speech at the conference, which was organized by the International Sematech Manufacturing Initiative. TSMC's Fab 12 in Hsinchu will also be expanded, to 70,000 wafers/month. The larger fabs are more efficient, Liu said, because the costs of the automated material-handling and computer-integrated manufacturing systems can be spread out over more wafers.
"Gigafabs have better cycle times because there are fewer equipment bottlenecks," Liu said. "Compared with three years ago, when we talked about 25,000 wafers for a 300-mm line, we now plan for higher throughput. We are getting bolder and more aggressive. This comes at the request of our big customers, who want us to be more flexible."
'Adapt the line'
Christopher Conley, associate staff engineer at Nikon Precision Inc., said in an interview that small fabs often have a lithography tool "tuned to a boutique process or to one particular mask layer. If one machine goes dead, the whole line is halted. In a gigafab, they can adapt the line [if a machine goes down] and rearrange the work in progress to keep the line going."
Hutcheson of VLSI Research said that fab costs are not rising all that much, if viewed from the perspective of how many square inches of silicon can be processed for a given number of dollars. "The cost of R&D is what is really killing a lot of these people," he said. "A 65-nanometer process can cost more than $1 billion to develop, and that is creating new business models based on consortium-style development."
TSMC's Liu said that revenue growth for the semiconductor industry has slowed to about 10 percent a year, down from a 15 percent compound annual growth rate earlier. The semiconductor content in systems has become saturated, he said, resulting in growing pricing pressure.
Hutcheson said that VLSI Research is tracking far fewer designs than it was five years ago, with both new and "revised" designs those in which a chip is modified or upgraded declining in number. In 2000, VLSI Research counted 33,039 designs, but that number has plummeted to 18,083 this year. For the next five years, Hutcheson said that designs will decrease at a rate of - 8 percent annually.
"Design costs are exploding. In the old days a company could design an ASIC for one product. You can't do that now. And in consumer electronics, there is a very low hit ratio" of successful products, he said.
"The key constraint to growth is design productivity," Hutcheson said in an interview. "All of the design-for-manufacturability steps have to be completely automated. The idea that the designers should learn to use DFM tools is completely insane, because you want your designers to focus on designing the circuits, not on DFM stuff related to optical proximity correction and those kinds of things."
Some companies are figuring out how to do 65-nm designs and are keeping defect densities at historical lows, he said. Other companies with fewer resources are falling further behind, particularly as 300-mm wafer fabs grow so expensive.
"There is a huge difference in yields between the leaders and the followers when it comes to chip manufacturing," Hutcheson said.