SANTA CLARA, Calif. As chip designers, Kaushik Sheth and Egino Sarto struggled to fit silicon into cost-effective packages. Now they're trying to convince other chip designers to adopt a "package-aware" IC design flow.
Sheth and Sarto founded Rio Design Automation Inc., which will announce plans this week to provide software that lets chip designers optimize the placement of I/Os, bumps and pins and to "synthesize" interconnects between I/Os on different dice. The highly automated software will cut weeks off the design cycle, minimize die sizes and reduce package costs, the company said.
The larger question posed by Rio is whether, and to what extent, chip designers should be involved in packaging. Rio's software won't require designers to become packaging engineers, but it will bring a "what-if" packaging analysis capability into the design cycle before, during and after layout. "Chip design and package design have always been two separate camps," said Sheth, who is Rio's CEO. "It needs to come together in one engine to come up with the right optimizations and really solve the problem."
It's a grand vision, and it comes with some strong support. Rival EDA companies Cadence Design Systems and Magma Design Automation have invested in Rio, as have two well-known EDA "angel" investors, Atiq Raza and Andy Bechtolsheim.
At Magma, where Rio has an OEM relationship, a customer was recently able to cut its die size by 20 percent using Rio software in a Magma flow, said Sameer Patel, director of Magma's design implementation business unit.
"As the number of I/Os on a chip keeps increasing, designers need some kind of solution that can help them evaluate what will be the best package for their design, and what will be the best location for the I/Os to minimize the die size and keep package costs low," Patel said. While people actually running synthesis or layout may not be concerned with packaging, he said, somebody on the design team always is, and that person needs a what-if analysis tool.
"Chip designers don't have to become package designers, but designs do have to be package-aware," said Anant Agrawal, vice chairman of fabless semiconductor company InSilica and an adviser to Rio. Chips at 90 nanometers and below are using more and more serial, high-speed I/Os, he said, posing the kinds of packaging challenges that high-end CPU chips have faced for years.
But Daya Nadamuni, chief analyst at Gartner Dataquest, said it's unclear how many designers will need Rio's solution, and whether they'll be able to get the models they need from foundries. The need for package-aware design is greatest for chips at 500 MHz or more, or for stacked dice or flip chips, she said.
The need for IC/package "co-design" has been recognized for some time. One reason: the emergence of high-pin-count ICs. When chips have 1,000 or more I/O pins, it's hard to manually put them in the right places to minimize die and package costs.
Worse, signal integrity and power problems can easily ripple through the chip, package and board, sometimes causing systems to fail. Solutions may require a look at the entire system. For example, it may be better to optimize driver outputs at package pins rather than silicon pads.
Nozad Karim, vice president of application engineering at assembly house Amkor, is not affiliated with Rio but has been a strong advocate of package-aware IC design. "The voltage of the silicon is going down, and the current density is going up, so the power grid structure needs to be optimized so the person designing the die gets enough current with the proper impedance," he said. "Without that, the voltage is going to fluctuate."