Santa Cruz, Calif. A transatlantic development effort spearheaded by Synopsys Inc. and ARM Ltd. has resulted in the Verification Methodology Manual (VMM) for SystemVerilog, which not only promises to help bring the SystemVerilog language to life but to create some new standards as well.
The book, written by Janick Bergeron and Eduard Cerny of Synopsys and Alan Hunter and Andrew Nightingale of ARM, provides rules and recommendations for verification planning, testbench infrastructure, assertions, coverage-driven verification, system-level verification and processor-integration verification. It was published in late September by Springer Science and Business Media.
But the real impact of the VMM may lie in its attempt to create a standard for verification components in SystemVerilog. Appendices outline a VMM standard library, VMM checker library, Extensible Verification Component (XVC) standard library and software test framework. Synopsys is providing a source code license for the VMM standard library for
customers of its VCS simulator and for members of the SystemVerilog Catalyst program, which represents EDA and intellectual-property (IP) vendors.
Bergeron, a Synopsys scientist, likened the VMM library to the IEEE 1164 VHDL standard, which set forth a standard logic package for VHDL, allowing models to become interoperable. "That's what I hope this [VMM] methodology will do for block- and system-level verification, so we can create a compatible ecosystem of verification products that can interoperate," he said.
The book will be useful for anyone writing a testbench in SystemVerilog, said Bergeron. "If you want to take advantage of the features and the power put into the language, I think the VMM will allow you to adopt those techniques in an efficient and scalable way, without having to spend several man-years of effort and mistakes in learning how to use it better."
SystemVerilog is more than just another version of Verilog it's a design and verification language combined in one. And it represents an object-oriented approach that's new to many designers, noted consultant Stuart Sutherland, the president of Sutherland HDL Inc. (Tualatin, Ore.).
"I frequently encounter engineers who, like myself, come from a background of having written testbenches in a very structured manner using traditional HDLs," Sutherland said. "It is a daunting task to make the transition to
an abstract, object-oriented verification methodology. The VMM and accompanying source code provide a great starting point for us old-fashioned engineers." Sutherland's one gripe: The authors assume the reader already understands the concepts of object-oriented programming.
Synopsys' competitors are less impressed with the project. "It's not clear that the VMM delivers the openness, flexibility and broad application, from system to blocks, that our customers are looking for," said Jan Johnson, director of verification methodology at Mentor Graphics Corp.
Methodology and verification IP reuse guidelines are essential, but one size does not fit all, said Steve Glaser, vice president of marketing for Cadence Design Systems Inc.'s verification division. "It is not yet clear how comprehensive the [VMM] reuse guidelines are, including how they enable block-, chip- and system-level reuse and map to all tools in a flow," he said.
As for the VMM library as a standard, "We are interested in standards based on proven foundations, are truly open and become widely available through a standardization process that consolidates the best from multiple donations," Glaser said.
According to Bergeron, the Verification Methodology Manual effort included 21 people who were directly involved in creating content, and 41 reviewers. The four main authors, as he noted, all had day jobs. The kickoff meeting took place in early 2004 in Boston.
"We had regular conference calls once a week, quite a few e-mails, and an exchange of Word and Framemaker documents in back-and-forth editing sessions," Bergeron said. "It was a lot of effort to get a cross-Atlantic authoring team to come up with something that looks consistent."
"One pleasant surprise when the teams met the first time was the huge amount of common ground on ideas," said author Hunter, who is the design and verification methodology program manager at ARM.
In addition to the writing, Bergeron said, there was a lot of code to develop and test. "And there was a whole tool-support team that had
to deliver the tools to support this methodology, so we could try what we were saying needed to be done," he said.
"It's not just writing a book," noted Hunter. "We had to make sure we had compatible VCs [verification components] between the two companies."
The effort took longer than expected. When Synopsys and ARM announced the project in February 2004, they said the VMM would be available at the Design Automation Conference that June. A first draft was available for reviewers, but not a published book.
"We wanted to make sure we had customer reviews and that things got tried on real software," Bergeron said. "Rather than coming up with a book that would have to be revised six months down the road, we wanted this lined up with tool support as well." The book does not assume the use of ARM IP or Synopsys tools, the authors insist. However, the software has been tested on Synopsys tools. Precompiled versions of the VMM library will be shipped with Synopsys' VCS simulator and its new Pioneer-NTB testbench product (see Sept. 26, page 48).
A standard library
>With SystemVerilog defined as a language standard, why is there a need for a standard VMM library? Bergeron gave a practical example: creating high-level transactors for higher-level protocols in a PCI Express or USB design.
"By providing a well-defined mechanism for writing transactors, people can start using higher-level transactor functionality that's not tied to physical implementation," Bergeron said. "But in order to do that, we need a well-defined transaction-level interface and a well-defined mechanism so you can make a transactor do what you need it to do."
The VMM standard library has two sets of functions, Bergeron said. One is a set of base class libraries offering standard functionality on a protocol-specific basis. The other is a set of components every testbench needs, such as issuing events, broadcasting scheduling and exchanging transaction-level models.
Asked whether Synopsys will bring the VMM library before a standards body, product-marketing manager Tom Borgstrom said that's something the company will "consider down the road."
A VMM checker library includes more than 50 assertion checkers that can be instantiated in SystemVerilog code.
The XVC library, which comes from ARM, is aimed at system-level verification. The software test framework provides library components that allow people to write test software in a more abstract way.
ARM and Synopsys have set up a Web site at www.vmm-sv.com that provides further information about the methodology and the book.