San Jose, Calif. As the CAD community grapples with emerging technologies like silicon nanowires, biofluidic microchips and DNA self-assembly, one major question emerges: How are we going to design this stuff? That challenge was brought before researchers last week at the International Conference on Computer-Aided Design (ICCAD) here.
When noted researchers in nanotechnology and bioelectronics described design challenges and requirements for design tools, the CAD community listened. "There is a certain maturity in traditional CAD, and we're looking for a way to extend our focus," said Soha Hassoun, ICCAD program chair and associate professor of electrical engineering and computer science at Tufts University. "There are a lot of exciting challenges in nanotechnology that we need to look at."
Andrť DeHon, associate professor of computer science at the California Institute of Technology, said, "If I'm looking at what I'll be designing 10 years from now, there will be changes in methodologies and in what I need from CAD."
One big issue for DeHon and other researchers is defect tolerance: As devices become very small, they are going to have relatively high defect rates.
Another message from ICCAD is that CMOS scaling is heading toward the end of the road. "The lithography approach will fail very soon," said Konstantin Likharev, professor of electrical engineering at Stony Brook University. Because the usual lithographic patterning is just too expensive below 20 nanometers, he said, it's time to look at "bottom-up" approaches using objects at the molecular level.
An example is the molecular single-electron transistor, which traps a molecule between the source and the drain. A change in the number of electrons in the molecule causes switching to occur. While such devices are promising, yields are presently very low, Likharev said.
The real opportunity, he said, is for "hybrid CMOS/nanocircuits." These could combine the functionality, reliability, and fab and EDA infrastructure of CMOS with the very high density achievable with nanotechnology. To this end, several research groups have developed nanowire crossbar architectures with two-terminal programmable diodes at every crossbar point.
Stony Brook's so-called CMOL architecture uses two-terminal, single-electron latching switches at each point of a metallic crossbar. To allow access to individual nanodevices, it's tilted relative to the CMOS circuitry. CMOL has been applied to memories and FPGA fabrics. Using "rudimentary CAD tools," Likharev said, researchers managed to create an FPGA fabric with a hundredfold area advantage.
Design challenges for this type of architecture include individual addressing of nanodevices, defect analysis and defect tolerance. "We need better CAD tools," Likharev said. "There is a good opportunity for this [design automation] community to do some important work while the technology is still in its infancy."
DeHon, who co-authored a paper with Likharev, described research with silicon nanowires that can be 3 nm in diameter and several microns long. The electrical properties can be controlled through selective doping. The nanowires are "grown" and aligned on liquid film, and are then transferred to a substrate.
When nanowires are assembled with unique codes, they can form an address decoder. If individual nanowires are kept relatively short, this technology can be used to construct memories or logic. DeHon showed an example of a nanowire-based PLA that offered density improvements ranging from 32 to 1,000 times in benchmark circuits.
A key EDA requirement for this type of architecture, DeHon said, is statistical analysis, prediction and optimization. Other necessary capabilities are defect calculation, location and mapping, allowing designs to be customized around defects. Finally, "lightweight" online error detection will be required to catch defects and transient errors that occur during operation. "I see an increasing role for CAD, especially dealing with post-fab issues," DeHon said.
Navin Srivastava, PhD candidate at the University of California at Santa Barbara, presented research on "realistic" RLC (resistance, inductance, capacitance) modeling of carbon nanotubes. Realizing these models is a first step toward building CAD tools for such devices, he said.
Previous modeling efforts, Srivastava said, did not provide realistic RLC calculations for bundled carbon-nanotube interconnects, did not allow for imperfect contacts, and used unrealistic drivers and loads. A "fair comparison" to copper, he said, shows that carbon-nanotube bundled interconnects don't provide much performance improvement at the local level, but do show a significant improvement for long, global interconnects.
Since nanofabrication is a very tough challenge, self-assembly the spontaneous organization of matter under controlled conditions is an attractive alternative. Paul Rothemund, a senior research fellow at the California Institute of Technology, showed how DNA self-assembly can generate arbitrary patterns and shapes at resolutions down to 6 nm.