Fremont, Calif. Asynchronous logic design is becoming one of the better-kept secrets in the chip design community. To most engineers, asynchronous design is a good source of thesis topics but is of no importance to actual design practice. Conventional wisdom calls the technique unproven and inherently unreliable, holds that it has never shown a convincing advantage over standard synchronous design and points to a lack of support tools.
In fact, a growing number of advanced design teams are quietly employing asynchronous practices today quietly, because most of them consider the approach a differentiating advantage they are not particularly interested in sharing. So while most of the industry and all of the EDA community looks the other way, asynchronous-logic design is rapidly becoming a mature technology among a select few.
One of the earliest companies to embrace asynchronous logic publicly was Fulcrum Microsystems Inc. The Calabasas Hills, Calif., company initially tried to interest the industry in a tool chain that would make it possible for conventionally trained designers to produce clockless logic circuits. Most designers weren't interested.
So the company used its own tools to develop a fully asynchronous crossbar switch technology and incorporated that into the PivotPoint SPI-4 switch chip, now used by about 15 vendors as the bus switch on network-processing boards.
Based on this success, Fulcrum is deploying essentially the same crossbar core in another application, this time a family of 10-Gbit Ethernet switches called FocalPoint supporting up to 24 ports.
The switch fabric itself dissipates very low power, and the power is always proportional to the data rate actually passing through. So no elaborate techniques unsupported by EDA tools like dynamic voltage scaling are necessary. The asynchronous paths are sufficiently fast that the IC can offer full 10-Gbit speed and 200-nanosecond total latency through the chip in a conservative, low-leakage 130-nm process.
Fulcrum has learned some lessons about using asynchronous design selectively, however. "In FocalPoint, the registers and Rambus Ethernet ports are traditional, synchronous designs," said company president and CEO Robert Nunn. But the majority of the chip "the parts that determine the performance and power consumption, including the crossbar and its SRAM are asynchronous designs."
One more public proof point in the news of late comes from another longtime async advocate, the Handshake Solutions business line within the Philips Technology Incubator. Handshake too has developed its own asynchronous flow and used it primarily in the smart-card market, where the extremely low power and broadband electromagnetic-radiation pattern make it an ideal choice.
Recently Handshake announced that an outside company, Malaysia Microelectronics Solutions, had licensed Handshake's 8-bit microcontroller core for use in its own chip designs. It may sound like any other design win, but a traditional, independent fabless chip company's licensing of a fully asynchronous MCU core is a ratification of sorts of the advantages and reliability of the Handshake design.
A third point is far less public. Octasic Semiconductor (Montreal), one of the major players in echo cancellation, speech optimization and packet management for voice-over-packet applications, told EE Times recently that its proprietary architecture employs unclocked pipelines to achieve a combination of very high throughput, insensitivity to process variations, low power and excellent silicon efficiency. The company has developed its own asynchronous-design tools, according to Octasic CTO Doug Morrissey, and is quite comfortable with the techniques.
Quietly, then, the idea is spreading. And so, among insiders, is the perception that clockless logic design may be the only way to tame the combination of high static and dynamic power, process-induced timing variations, low signal integrity and limited performance endemic to future CMOS processes.
Too bad about the commercial tools.