COLORADO SPRINGS, Colo. Startup Enigma Semiconductor Inc. has introduced a packet-switching chip set, HybriCore, that provides 280 Gbits/sec of bandwidth across backplane applications.
Enigma (Santa Clara, Calif.) chief executive Rob Sturgill said the architecture’s native packet implementation makes it more appropriate for video or Voice-over IP applications than switching chips based on internal cell structures.
“Our team developed HybriCore with the assumption that if data arrives in packet form, it should be transported across the backplane in packet form,” Sturgill said.
HybriCore is based on a byte-aligned crossbar switch that enables system designers to choose arbitrary byte-level scheduling boundaries, without the cell tax normally associated with the headers of asynchronous transfer mode cells or time-slot architectures.
Enigma has licensed serial-link technology from Rambus Inc. to add adaptive features to traditional serializer/deserializer cores. The links start with a serdes and PLL-based reference clock, but add decision-feedback equalization to support data rates from 2 to 10 Gbits/sec.
Sturgill acknowledges that Enigma will compete with switching solutions based on Rapid I/O, Infiniband, PCI Express Advanced Switching, and even Ethernet implemented as a switched serial link. But the combination of byte-aligned packet switching and adaptive serial links will suit Enigma’s method of backplane switching or triple-play services with voice and video, Sturgill said.
While skeptics might say the Layer 2/3 Ethernet switch market has commoditized, Enigma is betting that new backplane opportunities will emerge from the convergence of metro-edge routers, multi-service switches, Layer 3 switches, and SAN switches. While Enigma is eyeing other crossbar-based switch concepts in development, Sturgill anticipates little direct competition from shared-memory switches, due to the latencies typically seen in such ICs.
The Enigma solution, sampling in the first quarter, will use a crossbar switch on the system switch card, and a fabric manager on the line card that achieves 98 percent data link utilization over the backplane. Enigma promises 280 Gbits/sec per switch, or 2 Tbits of full-duplex nonblocking packet traffic supported across the backplane.
More information on the CMOS devices will be disclosed at sampling, but Sturgill said that on-chip memory will not be a limiting factor, since small on-chip buffers will be used.