TOKYO Toshiba Corp. has fabricated a 128-Mbit capacitorless DRAM on an SOI wafer and verified operation of the chip.
Toshiba reported on the 128-Mbit capacitorless DRAM design and result of the simulation at the International Solid State Circuits Conference (ISSCC) last February. At the International Electron Devices Meeting this week, Toshiba reported on the operation of the chip, claimed to be the largest density capacitorless DRAM fabricated.
Capacitorless DRAM employs a floating body cell generated underneath of the gate insulator film to store data instead of a capacitor used in conventional DRAM. Some companies, such as Innovative Silicon Inc. and Renesas Technology Corp., announced prototypes in addition to Toshiba, which started researching the floating body cell memory in 2000.
The 128-Mbit capacity is the largest density among these efforts, said Takeshi Hamamoto, chief specialist at Advanced Memory Device Technology Department of Toshiba SoC research & Development Center.
"The 128-Mbit density is large enough for technological evaluation. Though it is totally dependent on practical applications, we would be able to put the LSI to use in three years if necessary," Hamamoto said.
The chip was fabricated on a 90-nm CMOS process with six layers of metal. The cell size is 0.17 square microns, about half of a conventional DRAM cell area.
To fabricate the device, Toshiba engineers introduced a new well design optimized for the array layout and copper wiring for bit lines and source lines. The copper wiring helped the chip achieve a writing time of 10 ns and reading time of 20 ns.
The number of fail bits is 36 per 32-Mbit area, which Hamanaka said indicated a good die.
Having completed the LSI development, Toshiba will continue testing the chip in bad conditions to improve the reliability.