SAN FRANCISCO Sequence Design Tuesday (Feb. 28) released the next generation of its PowerTheater design suite, targeting requirements for wireless, mobile, and large system-on-chip (SoC) designs below the 90 nanometer node.
Sequence (Santa Clara, Calif.) said new PowerTheater features enhance its RTL power analysis capabilities and usability. Enhancements include peak power analysis, power gating, voltage domains, expanded support for RTL and gate-level power estimation of multiple voltage domains and support for SystemVerilog.
"Below 90 nanometer, power dominates all other issues," said Vic Kulkarni, Sequence president and CEO, in a statement. "PowerTheater is unique in its ability to analyze and optimize power at RTL, where decisions are made that determine 80 percent of a chip's total power budget, leading to better results and faster time-to-market."
PowerTheater provides gate-level, time-based power analysis, providing a view of power dissipation as a function of time within a waveform display, Sequence said. The product has strong links to Sequence's CoolTime cell-based voltage drop analysis tool, as well as other dynamic voltage drop tools, the company said.
Pricing information was not disclosed.