SAN FRANCISCO Productivity the cost in time and resources that it takes to complete a chip is the dominant issue in IC design today, according to John Chilton, senior vice president and general manager for Synopsys Inc.'s Solutions group.
While the design gap between what the market demands and what the IC industry can supply is growing, Chilton told audience of mostly design and verification engineers at last week's Design & Verification Conference (DVCon) in Santa Clara, Calif, the limitation has seemingly shifted from capability to productivity.
"The good news is that we're not hearing so much that we won’t be able to get chips to work, or work fast enough, it’s just that we won’t be able to design them within a reasonable time-frame and budget," Chilton said.
For a small fraction of chips, Chilton said, the market is so large that it doesn't matter chip makers will get them out at all costs. But for the vast majority of devices, the productivity issue is a "crisis," Chilton said.
Whereas quality-of-results was once the dominant goal for EDA companies, today it is productivity, Chilton said. But the problem is that productivity in IC design is difficult to even measure, much less improve, he said. Synopsys' Services group, he said, has been working for a couple of years on a set of metrics to track the cost of design and determine if the industry is getting more efficient. Design size, performance, process node, libraries and intellectual property (IP) maturity have been determined to be the main factors in design productivity, Chilton said.
Comparing the building of chips to the building of skyscrapers, equating cells to conference rooms and cubicles, and design-rule checking and layout-vs.-schematic to building regulations, a 20-million gate IC would contain 628 times the floor space of Taipei 101, the tallest building in the world, Chilton said.
Adoption of SystemVerilog for verification and SystemC to enable earlier software development will enhance design productivity, Chilton said, as will making use of speed offered by multi-processor tools. Next-generation place-and-route tools and configurable design environments will also increase productivity at the infrastructure level, Chilton said.
Chip-level IP, Chilton said, created in partnership by multiple vendors, and lifecycle productivity level enhancements hitting better markets earlier will also contribute to making IC design more productive. Ultimately, Chilton said, it is possible for the industry to increase productivity eight fold through a combination of infrastructure-, project- and lifecycle-level enhancements.
To achieve this, Chilton said, requires adopting the best tools and methods and a "divide and conquer" approach at the project level especially by using high-quality IP to create new productivity for building a better business.
Chilton said more than half of the challenges facing today's system-on-chip (SoC) development are not design-related, but "project-related." Chilton referenced a recent survey conducted by Synopsys at the Synopsys Users Group and FSA Expo in October 2005, which found that more than 50 percent of respondents' issues with SoC creation could be considered project-related. While the top concerns were the "usual suspect" design items timing/signal integrity closure and functional verification project issues such as concurrent flow development, and the quality of third party intellectual property (IP), EDA tools and libraries also ended up in the top 10, Chilton said.
Part of the design productivity problem in recent years, Chilton said, was that original third-party IP core were designed and sold without proper testing, validation and support. Proper IP core creation is an expensive undertaking that demands a substantial breadth of experience, tools and resources, Chilton said.