Portland, Ore. -- Defects in fabrication and errors during operation will become a fact of life for electronic circuits at the nanoscale. To compensate, researchers are crafting schemes to correct fabrication defects and processing errors on the fly. Georgia Institute of Technology, with funding from Intel Corp., is pioneering probabilistic CMOS to trade off processing errors for cooler running temperatures. And Hewlett-Packard Co. recently demonstrated a chip that uses massive redundancy and automatic recovery to compensate for fabrication errors in a 100-Gbit/cm2 nanowire storage array.
"In the future, chip manufacturers will have to deal with the reality of defects in their circuits," said Stan Williams, a senior fellow at Hewlett-Packard Research (Palo Alto, Calif). "By using a crossbar architecture with 50 percent redundancy, we believe it will be possible to fabricate nanoscale circuits with nearly perfect yields even though the probability of broken components is high."
Hewlett-Packard's current demonstration used nanoimprint lithography to fabricate 15-nanometer-wide wires with just 19 nm between their edges. Using a superlattice-pattern transfer technique, the researchers fabricated a 300-layer GaAs/AlGaAs array of 150 silicon nanowires with just a 34-nm pitch. By using the same imprinting mold to pattern a second array of identical nanowires above the first set, but at a 90° angle, they produced a platinum nanowire crossbar switch with a cell density of 100 Gbits/cm2.
HP worked around the inevitable fabrication errors inherent in such high-density circuitry by using 50 percent redundancy and an automatic demultiplexer algorithm drawn from coding theory to reroute defective connections. Using a code similar to those in digital cell phone systems and deep-space probes, the demultiplexer for the incredibly dense crossbar array was able to route around inevitable defects.
HP predicts that circuit densities will necessitate the use of its scheme for chips produced in about six to seven years' time. Previous work has shown that crossbar arrays can perform all the logic functions now realized with transistors. Last year HP researchers demonstrated a scheme consisting of two control lines crossing a signal line and connected by a switchable molecular component. This simple switch can perform the logical NOT operation and can also restore signals to their specified levels. Since any Boolean function can be expressed in terms of NOT operations, an array of such switches can implement general logic operations.
Instead of correcting errors with redundancy, Georgia Institute of Technology researchers, with funding from Intel and the Defense Advanced Research Projects Agency, propose harnessing errors to lower chip temperatures. In conventional ICs and computing architectures, logical values must be correct--that is, they have a probability of 1 for their value. In the Georgia Tech work, the probability of a correct output from a transistor is only required to be some probability p, which is less than 1. Then the probability that it is the wrong value becomes 1-p . Krishna Palem, an EE professor and founding director of the university's Center for Research in Embedded Systems & Technology, has developed a type of logic he calls probabilistic CMOS (PCMOS) that can achieve valid results with a lower probability figure for logical values.
Starting over from scratch with thermodynamics and statistical mechanics, Palem has shown that PCMOS can achieve valid results with far less energy than traditional logic. The new approach is particularly suited to a growing body of algorithms that use probability as a computational component.
"We've gotten energy savings of a factor of more than 500 using ultra-energy-efficient embedded architectures based on probabilistic CMOS," said Palem.
PCMOS may also head off the looming heat crunch as circuits increase in density--one of the biggest problems with achieving nanoscale circuit densities is getting rid of the heat generated. And the probabilistic approach may be the only option as shrinking transistors become more and more susceptible to noise, the Georgia Tech researchers believe.
PCMOS copes with errors with a statistical approach that classifies errors as noise. The circuits harness noise by averaging the results of data streams the chip is processing. Although not applicable to all types of information processing, many signal-processing techniques can work by planning on a certain noise level. The specific algorithm demonstrated in the current work was able to decompress a video data stream with no visible image degradation while running more than 500 times cooler than a normal video chip.
"Probabilistic architectures extend PCMOS to different kinds of computing," said Palem. "Our gains ranged from a factor of 10 to a factor of more than 500 over conventional architectures."
Palem has developed a system-on-chip architecture in which a probabilistic coprocessor handles the less-than-perfect logic execution while the remainder of the chip uses conventional always-correct logic.
Using a particular architecture called a probabilistic cellular automata as a benchmark system, the Georgia Tech researchers used HSpice to simulate two circuit implementations--one based on conventional logic and the other on PCMOS. The benchmark is expressed in terms of the energy consumed in joules multiplied by the total number of clock cycles. Results of running probabilistic cellular-automata algorithms for pattern recognition and string matching were dramatic, with the PCMOS architecture achieving a factor 1,900 over conventional logic in terms of energy times performance.
The team also demonstrated a random-number generator that it calibrated against the current method proposed by the National Institute of Standards and Technology. Its PCMOS architecture produced higher-quality random sequences than the standard NIST method.
Next, the Georgia Tech researchers plan to create a library of video and audio signal-processing algorithms to demonstrate that its PCMOS architecture can be widely applied. -- Chappell Brown contributed to this report.