SAN FRANCISCO Top-tier EDA vendor Synopsys Inc. Monday (March 20) laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout its suite of design and verification products.
Synopsys claims that more than 150 companies are already using the company's SystemVerilog solutions in design and verification. Steve Smith, senior director of platform marketing for Synopsys' verification group, said the company expects the availability of a complete SystemVerilog flow to dramatically increase the number of companies using SystemVerilog.
"We expect the floodgates to open," Smith said. "Thousands of users are chomping at the bit to get started."
As part of the flow, Synopsys (Mountain View, Calif.) introduced SystemVerilog verification intellectual property (IP) support for its VCS verification library.
SystemVerilog, which was approved as a standard by IEEE last November, is said to express complex designs more succinctly and accurately, enabling designers to capture critical design attributes with assertions and develop advanced coverage-driven, constrained-random testbenches.
A survey conducted by Deepchip.com moderator John Cooley last year found that 44 percent of 338 respondents planed to use SystemVerilog within the next year.
Synopsys products supporting the SystemVerilog standard now span the Galaxy Design and Discovery verification platforms, including Design Compiler for logic synthesis, the VCS comprehensive verification solution with Native Testbench, the Pioneer-NTB SystemVerilog testbench automation tool, the Formality equivalence checker, the Magellan hybrid formal analysis tool, and the Leda programmable RTL checker, Synopsys said. SystemVerilog support is also provided in the assertion-checker and base-class testbench building-block libraries that ship with Discovery products as well as in the VCS Verification Library, the company said.
“Synopsys has been the key driver of SystemVerilog since day one,” said Aart de Geus, Synopsys chairman and CEO. “We have donated key testbench and assertion constructs to the Accellera language standards organization and have continued our industry leadership by working with a wide range of companies to complete the Accellera specification and to achieve IEEE standardization in record time."
According to Smith, early adopters of SystemVerilog have been using the language through multi-vendor flows of point tools cobbled together, sometimes painstakingly. The availability of a cohesive, integrated flow will spur more companies to employ the language, Smith said.
"There is no really rational, good excuse not to use it now," Smith said.
In a separate announcement, Synopsys said VCS verification library, containing DesignWare verification IP, is the first to support testbenches created using SystemVerilog and the coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog, the manual co-written by Synopsys and ARM Holdings plc.
According to Synopsys, the SystemVerilog verification IP can decrease the cost of testbench development, speed the time to reach coverage goals and reduce risk.
Current customers of DesignWare Verification IP can gain access to the new functionality at no additional charge by requesting the SystemVerilog version from the Synopsys Web site, the company said.