SAN FRANCISCO Design optimization technology Zenasis Technologies Inc. said Monday (March 27) it has expanded its ZenTime transistor-level optimization product family with the additions of ZenTime-GT, ZenTime-AT and ZenTime-PT.
Zenasis (San Jose, Calif.) said the new products automate standard cell design optimization for timing, area and leakage power, respectively, accelerating design closure for high-speed standard cell designs.
According to Zenasis, timing closure is a continuing challenge for high-performance standard cell designs. Leakage power, which is increasing exponentially, can no longer be ignored, Zenasis said.
Intellectual property (IP) core integration and migration further complicate the process, the company said, and the limitations of traditional approaches result in multiple, lengthy design iterations and a substantial amount of manual intervention.
Zenasis said its ZenTime products, utilizing patented hybrid optimization technology to analyze and optimize standard cell designs at the logical, physical, and transistor levels, achieve many of the benefits of custom design in a manner transparent to the designer.
“There are counterbalancing forces that must be managed with high-speed nanometer designs,” said Dennis Harmon, Zenasis president and CEO, in a statement. “Our ZenTime products automatically resolve designers’ conflicting optimization goals within project deadlines, and allow them to push their quality of results to the design limit while reducing product costs.”
ZenTime-GT enables designers to achieve performance improvements without changing their existing process technologies to smaller, lower yield geometries, Zenasis said. The tool employs multiple timing optimization techniques, the company said, including buffer insertion, gate sizing for discrete drive strengths, pin permutation, the use of inverted logic gates and output stage sizing. ZenTime-GT is tightly integrated with placement and static timing analysis engines and can be plugged directly into existing standard cell design flows, Zenasis said.
ZenTime-AT is said to work in conjunction with ZenTime-GT to manage the area tradeoffs associated with meeting timing constraints. Following timing optimization with ZenTime-GT, ZenTime-AT recovers area impacted by timing optimization as well as from positive slack points, Zenasis said, enabling designers to control product cost.
ZenTime-PT works in conjunction with ZenTime-GT to improve leakage power tradeoffs, Zenasis said. Following timing optimization with ZenTime-GT, ZenTime-PT reduces the leakage power on the non-critical paths, the company said. The power optimization step enables efficient use of low-voltage cells in a multi-voltage design, the company said, resulting in longer battery life.
Zenasis said all three of the new Zen Time products are tightly integrated into existing standard-cell design flowsthey are intended for use following the logic and physical synthesis stage. The input to ZenTime products is a Verilog netlist, DEF and SDC files, and library information such as GDSII, .LIB, LEF, Verilog and Spice netlists, the company said. ZenTime products output an optimized Verilog netlist and DEF, plus GDSII, .LIB, LEF, Verilog and Spice netlists for the cells created on-the-fly, Zenasis said.
ZenTime-GT, ZenTime-AT, ZenTime-PT and ZenTime-XT production versions are available immediately, Zenasis. Pricing information was described as "flexible," but not specifically disclosed. ZenTime’s product family runs on Linux and Sun-Solaris platforms.