After creating the carbon monolayer, the researchers used conventional photolithography steps, including spin coating on photoresist, and patterning with optical lithography and electron-beam lithography. Then they etched off the unwanted graphene, leaving behind the structures for test transistors and quantum-interference devices.
"So far we have built a transistor and several loop devices using conventional photolithography with our graphene material, but none of our designs is even close to being optimized," said First.
The researchers predict that it will be five to 10 years before they have fully optimized the process for patterning graphene, but by then they expect that it will be possible to completely integrate the carbon-based devices with conventional silicon chips. If they are right, as silicon chips start to take advantage of graphene films, they will begin to demonstrate ballistic electron transport plus the ability to process electron-wave interference properties.
"So far we have demonstrated a material with extremely high mobility and a well-defined road map showing how to create nanoscale electronic devices based on this material," said First.
"Even without optimization, we have demonstrated mobilities at room temperature of up to 10,000 square centimeters per volt-second," compared with 9,000 for gallium arsenide or 1,500 for silicon.
Today the smallest features of state-of-the-art silicon chips are 65 nm wide, but as this shrinks into the teens over the next decade, many problems are expected to block progress until they are solved. For instance, today dopants are implanted as defects in a crystalline silicon lattice to effectively control what kind of carrier it handles--electrons or holes. However, nanoscale features on future chips will be only a few atoms wide, making dopants difficult to implant uniformly.
"The problem with silicon chips when you get to nanoscale sizes is that dopants are not distributed evenly enough," said First. "Today, dopants-per-device fluctuate around a mean, but at the nanoscale the variation between devices can be huge. Instead of having device properties that fluctuate around a mean, the variations become that between a good device and bad device."
With graphene, on the other hand, the Georgia Institute of Technology researchers have shown that dopants do not have to be uniformly distributed throughout the nanoscale channel. Instead, they can be added along the edges of features so that only the length of the channel needs to be controlled.
"Ultimately, to get room-temperature operation requires having lines only a few nanometers in width," said First. "At that scale, the dopants which control the number and kind of carriers [electrons or holes] can be removed from the channel itself. The mobilities remain very high whether you use electron or hole carriers."
Some problems can also be solved by using carbon nanotubes as the channels of the transistor. For instance, IBM showed that by using different types of metals for gate, source and drain electrodes, it could avert problems associated with doping nanoscale materials. Unfortunately, the rest of IBM's carbon nanotube transistor--its gate, source and drain--had the same electron mobility as traditional silicon chips.
The Georgia researchers claim a method of imparting ballistic transport not only to the transistor channel, but also to the gate, source and drain.