A number of ISPD 2006 papers delved into timing analysis. Researchers from STMicroelectronics and the University of Montpellier (France) presented a technique that accounts for supply voltage and temperature variation. Arguing that a statistical approach cannot accurately capture deterministic voltage and temperature variations, the paper proposed using nonlinear derating coefficients for capture.
The method first uses Synopsys Inc.'s PrimeTime analyzer to run a basic timing analysis for a given corner. Next, all timings are recomputed for the temperature and supply voltages provided. Propagation delay values are computed using traditional timing-library files, and then the final delay values, including variations, are obtained.
The University of Maryland addressed a vexing issue for designers of nanometer ICs: How can you tell whether one design solution is better than another in the midst of process variability? Typically, a better solution is superior with respect to timing or cost. But process variations randomize the timing and cost, noted Vishal Khandelwal, a PhD candidate at the university.
Get out the shears
What's needed, he said, is a way to "prune" probability so as to discover the solutions that are probabilistically superior. The paper presented a "conditional" Monte Carlo technique using analytical bounds and a joint probability-density function that's computed mathematically.
Two papers looked at variation with respect to clock networks. The University of Arizona proposed a statistical-centering-based algorithm that improves skew tolerance to interconnect variations. It also described a variation-aware abstract topology-generation algorithm. The techniques claim to reduce skew violations by 12 to 37 percent.
The University of Texas at Austin proposed a unified algorithm for synthesizing a variation-tolerant, balanced, buffered clock tree with cross-links. Unlike previous link-based approaches, said UT professor David Pan, this work doesn't require expensive "tunable" buffers.
-- Richard Goering