Portland, Ore. -- Next-generation semiconductors aim to harness the ballistic electron transport capabilities of pure carbon nanotubes, but until now there has been no easy way to integrate the tubes with silicon chips.
Now IBM Corp. researchers think they have the solution--coat nanotubes with a ligand that only sticks to high-k dielectrics, then lithographically pattern the wafer with high-k dielectrics wherever transistor channels are wanted. The researchers showed that carbon nanotubes would self-assemble on the lithographically defined channels and that annealling boiled off their ligand coating, leaving behind arrays of carbon nanotube transistors.
Normally, when used as the channel for a transistor, carbon nanotubes are many times smaller than the source and drain electrodes--less than 1 nanometer, compared with tens or hundreds of nm. This makes it difficult to fabricate them using traditional lithographic techniques.
"All nanotube devices so far have been fabricated using e-beam lithography," but because of its low yield such lithography cannot be applied in commercial production, said Phaedon Avouris, an IBM fellow at the company's T.J. Watson Research Center (Yorktown Heights, N.Y). "The possibility of self-assembling them is one of the major reasons for our research in nano- tubes and other molecular devices," Avouris said.
"By putting a chemical group on the nanotubes, they attach themselves where we want them. Then, by a simple thermal-annealing process, the chemical group is nicely removed, and the resulting transistors have excellent electrical properties," Avouris said.
Avouris performed the research with fellow research center technical-staff members Christian Klinke, James B. Hannon and Ali Afzali.
The process runs on any standard CMOS semiconductor fabrication line.
In their proof-of-concept demonstration chip, the IBM researchers fabricated an array of nanotube transistors by patterning 40-nm-deep x 300-nm-wide aluminum lines on a silicon dioxide wafer, placing them where transistor channels were supposed to be. The aluminum was then oxidized to turn it into a high-k dielectric. Next, the chemically treated nanotubes, in an ethanol solution, were applied to the wafer. At this point, the nanotubes stuck only to the high-k dielectric pattern and not to the silicon dioxide substrate. Finally, the IBM team patterned electrodes for the source and drains of the transistors. The resultant demonstration transistors had a 400-nm channel length.
To engineer the perfect ligand to enable the nanotubes to self-align along lithographically defined lines of high-k dielectric, the researchers took advantage of two well-known chemical reactions. The first exploits the tendency of carbon nanotubes to coat themselves with aryldiazonium salts, a room- temperature reaction widely used to attach organic compounds to nanotubes. The team engineered an organic ligand using alkylhydroxamic acid on the inside (near the nanotube) and a dangling hydroxyl group that makes the nanotubes stick to metal oxide high-k dielectrics such as aluminum oxide.
The problem with nanotubes has been that their unique electrical properties "get destroyed when another chemical species is attached to them," said Avouris. "Now we have a reversible functionalization [attachment] of a chemical group to nanotubes that wants to bind to certain materials, such as hafnium dioxide or aluminum oxide [high-k dielectrics], but not to silicon dioxide."
The carbon nanotubes aligned themselves along the long axis of lines laid out in aluminum oxide, enabling 28 out of the total of 49 test transistors on the demonstration chip to be functional.