According to the researchers, the 12-bit, 100-ksample/s A/D represents an upper bound in performance required for most microsensor applications. Moreover, its sampling rate can be reduced arbitrarily to yield linear power savings, Chandrakasan said.
The architecture of an energy-efficient sensor node processor needs to be maximized for power efficiency. It thus uses a custom CPU and instruction set to minimize the instruction memory footprint. Dedicated blocks for interfacing to the A/D and radio, as well as for performing complex algorithms such as fast Fourier transforms, handle common tasks much more efficiently than CPU software. A direct memory access engine further reduces CPU load by efficiently moving data between the functional blocks and memory. In addition to dedicated hardware, ultradynamic voltage scaling (UDVS), in which supply voltage and frequency are varied to optimize energy, is an effective technique. A conventional dynamic voltage-scaling system operates at the lowest supply voltage that allows the throughput constraints to be met. Without speed constraints, a UDVS system further reduces the supply voltage to the subthreshold region, where energy is minimized.
Because of their high frequency of operation and wide bandwidth, RF circuits in a radio typically consume milliwatts of power and dominate the power budget of a wireless microsensor node. To achieve microwatt average power consumption and optimal energy efficiency, a radio can be duty-cycled by operating at a high instantaneous data rate and being turned off periodically. To realize an energy-efficient duty-cycled radio, it is important to minimize the idle-to-active startup time.
A key metric for measuring the energy efficiency of the transceiver is energy per bit, which is equal to the power consumption of the transmitter or receiver divided by the instantaneous data rate. MIT's radio achieves energy-per-bit ratios down to 0.4 nanojoule/bit in receive mode and 3.8 nJ/bit in transmit mode, the lowest demonstrated ratios in its class of low-power, short-range radios. These low ratios, combined with a fast receiver startup time of 2.5 microseconds, allow for energy-efficient operation, Chandrakasan said.
The transceiver operates in a single channel centered at 916.5 MHz and employs on/off keying modulation. A noncoherent, envelope-detection receiver architecture removes the need for a local oscillator and allows for a fast receiver startup time. On/off keying is well-suited for energy-efficient short-range wireless links, where circuit power consumption is often greater than the transmitted output power. The receiver power consumption scales from 0.5 to 2.6 mW, with an associated sensitivity ranging from –37 dBm to –65 dBm at a bit error rate of 10–3. The transmitter supports output power levels from –11.4 dBm to –2.2 dBm.