Like high-k, low-k dielectric films have made it into production to some degree. Low-k materials reduce capacitance and propagation delays within the interconnect layers of a device more effectively than mainstream silicon dioxide insulators, boosting overall chip performance in next-generation designs.
The effectiveness of a low-k material is measured by its dielectric constant. Silicon dioxide has a dielectric constant, or k-value, of 3.9. In 1999, the International Technology Roadmap for Semiconductors called for lower-k materials with values of 2.7 to 2.2. But the complexity of this technology caused the IC industry to push out those targets to 2007 or beyond.
The deployment of low-k has been hampered by integration problems with copper, and by packaging complexities and other factors.
A few leading-edge chip makers implemented the technology at the 90-nm node, reportedly with k values at 2.9 to 3.0. But instead of making a huge leap with low-k, chip makers are now taking incremental steps to extend the technology at the 65-nm node and beyond.
"We are trying to extend the baseline process as long as possible," said Vincent McGahay, senior engineer for the Exploratory Integration Semiconductor Research & Development Center (Hopewell Junction, N.Y.)
In a paper at IITC, IBM described a new version of its carbon-doped silicon oxide technology, dubbed SiCOH, which is said to have a “k” value” of 2.75. IBM’s proprietary film is devised by using chemical vapor deposition (CVD) tools. At present, IBM is using a CVD-based, low-k film with a “k value” of 2.9 to 3.0 as the baseline process for its 90-nm technology.
Some will extend the 2.7 to 2.8 “k-value” films to the 45-nm node and perhaps beyond. This is because low-k has simply hit the wall, said Mahesh Sanganeria, an analyst with RBC Capital Markets Inc. (San Francisco).
“I don’t see [low-k] going beyond 2.5,” he said. “The problem with low-k is the mechanical properties.”
Douglas C.H. Yu, senior director of the Advanced Module Technology Division for silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), was slightly more optimistic about the future scaling of low-k films.
In theory, low-k films based on CVD could be extended down 2.0 in terms of k-value, Yu said. Beyond that, chip makers could be forced to revisit rival technologiessuch spin-on, hybrid or air gapfor low-k formation, Yu said.
“We are still leaving our options open,” Yu said, “but I doubt it could be spin-on. However, the hybrid approach is more likely. The drawback is cost. You have more tools and process steps.”
The air-gap approach could be a candidate in the future. At IITC, several chip makers proposed air-gap techniques, including Hitachi, Infineon and Matsushita.
“At one point, everyone has to think about this,” he said. At present, TSMC (Hsinchu) is using a CVD-based low-k film from Applied Materials Inc. (Santa Clara, Calif.), dubbed "Black Diamond."
“For 45 nm, some device manufacturers are talking about 2.7 or 2.5 materials. Some want 2.0 or 2.3 materials,” said Taeko Ikegawa, PECVD technical marketing manager at ASM Japan K.K. (Tokyo), the Japanese subsidiary of Dutch-based equipment maker ASM International N.V.
“At the 32- or 22-nm nodes, we could see a convergence of spin-on and CVD. Air gap is very interesting too,” she said. “But I don’t think that the industry has a clear vision of the 32-nm node.”
One possible way to track the world’s largest producer of low-k-enable chips is to follow the roadmap of ASMI. ASMI is reportedly the main low-k equipment provider for Intel Corp. (Santa Clara, Calif.). Starting at the 90-nm node, Intel has been reportedly using AMSI’s CVD-based low-k film, dubbed "Aurora."
In a paper at IITC, the team of ASMI and Japan’s Semiconductor Leading Edge Technologies Inc. (Selete) described an Aurora-based film with a k value of 2.3 and a high modulus of 7.2 GPa. The technology is geared for the 45-nm node and beyond.