BURLINGAME, Calif. This week’s International Interconnect Technology Conference (IITC) brought to mind the famous 1951 science fiction movie classic: The Day the Earth Stood Still.
Or perhaps IITC was more like a new twist on the classic: The Day the Semiconductor Industry Stood Still.
Judging from papers and conversions at the conference here, it was shocking just how little the semiconductor industry has progressed in terms of two critical material technologieshigh-k dielectrics and low-k filmsfor use in next-generation chip designs.
The IITC papers presented a plethora of technology solutions that promise to enable chip designs down to the 32-nm node. But there were whispers in the corridors here among experts that high-k dielectrics and low-k films have separately hit a wall.
There is also a growing sentiment that high refractive-index materials for 193-nm immersion lithography not panning out, thereby implying that immersion will run out of gas at the 32-nm node.
What this further implies is that leading-edge chip makers may resort to a series of technology and economic tradeoffs in future scaling, thereby creating more incrementalor less aggressiveimprovements in next-generation chip designs.
For example, there is a growing sentiment that high-k materials for gate stacks in logic devices will not be ready for the 45-nm “half-pitch” node, as many leading semiconductors makers had hoped.
"It won’t be ready," said Hans Stork, senior vice president of silicon technology at Texas Instruments Inc. (Dallas), in a brief interview after a keynote address.
High-k has however made it into production. DRAM makers are using high-k for capacitor formation in memory designs, but the material remains a moving target for gate stacks in logic chips. Delays in high-k could force chip makers to extend conventional but lower-performance silicon dioxide and oxynitrides for the gate stack at the 45-nm node.
High-k dielectric materials were supposed to ride to the rescue by now, improving the electric-field strength in the channel and thus reducing leakage for a given dielectric thickness. The plan was to combine high-k with a metal gate, which would give a superior work function and eliminate the depletion region that forms at the bottom of the polysilicon gate electrode.
Due to their intricate composition, advanced films targeted for 45-nm high-k gate dielectricssuch as hafnium oxide (HfO), hafnium silicate (HfSiO) and hafnium silicate oxynitride (HfSiO/N)as well as metals like ruthenium, pose a challenge at the film-removal and other process stages.