Santa Cruz, Calif. -- Statistical timing analysis may represent the next major technology shift in nanometer IC implementation, but it's going nowhere fast without statistical timing models. Jim McCanny, CEO of startup Altos Design Automation Inc., believes he has a solution that will make statistical timing feasible.
Altos this week will introduce both itself and its first product, Liberate, a library characterization tool for standard cells and I/Os. While Liberate is aimed at today's static timing analyzers, Altos' real mission is to be an "enabler" of statistical timing, McCanny said. Later this year, Altos plans to roll out Variety, a characterization tool that can generate statistical models.
While current static timing analysis tools report best- and worst-case timing numbers, statistical timing analyzers evaluate process variations and return statistical distributions. A designer can thus evaluate the probability that a chip will reach a given performance target or yield. But as Altos is illustrating, statistical timing needs a supportive infrastructure to be successful--and it all starts with generating the models that statistical timing tools will consume.
"In order to do statistical timing, you need to be able to create a model that's accurate enough for any statistical variation," McCanny said. "We felt it was a niche that had very little attention."
Today's library characterization tools are running out of steam even for nominal static timing analyzers, McCanny said. Add in the process variations needed to support statistical analysis, and it may take 20 to 100 times longer to build a library, he said. Altos promises to introduce a new generation of superfast tools that will let designers characterize statistical libraries in about the same amount of time they currently spend characterizing nominal libraries.
Library characterization companies tend to be successful, but never grow very big, observed Gary Smith, chief EDA analyst at Gartner Dataquest. "Statistical characterization is the 'next' technology, so it's the next good market for a startup," he said. Statistical timing will become necessary at 45 nanometers and below, Smith said.
Statistical timing analyzers are available from such companies as IBM Corp., Magma Design Automation Inc. and startup Extreme DA. Those vendors have their own characterization capabilities. But Extreme DA is also partnering with Altos so that Altos can support Extreme DA's XT tool. "We don't see library characterization as our core business," said Mustafa Celik, Extreme DA CEO. "We don't know the details yet, but we heard that Altos' library characterization is fast."
Starting with expertise
Altos was launched in January 2005 by Ken Tseng, CTO, and Kevin Chou, vice president of research and development. Both worked for CadMOS Design Technology Inc., a provider of noise analysis software, before its acquisition by Cadence Design Systems Inc. in 2001. At Cadence, the pair became key developers for Cadence's popular CeltIC crosstalk analysis tool. McCanny, also a CadMOS alumni, joined Altos in July 2005.
After four years at Cadence, McCanny said, Tseng and Chou "decided that doing startups was a more exciting and rewarding way of life." Moreover, the Altos founders believed that there was a "gaping hole" in the market, McCanny said. "Existing tools struggled to get the libraries that people wanted at 90 nm," he said. "A lot of them are just Perl scripts that run Spice."
The problem, McCanny said, is that the libraries needed at 90 nm and below have a lot more "views." They use cells with multiple threshold voltages and dynamic voltage scaling, and even for nominal static timing analysis, designers must look at different voltage and temperature corners for those cells. "People may be looking for 60 different views--60 times more work than what they did before," McCanny said.
Altos' technology is based on what the company calls an "inside view" approach. In brief, the Altos tools look inside the cell to see how transistors are connected, and how the cell functions. The tools then eliminate redundant vector sequences that are electrically equivalent, thus reducing the amount of simulation needed. Further, Altos provides an integrated Spice simulator, so there's no need to call an external tool.
What's available today is Liberate, a library characterizer that supports the Composite Current Source model backed by Synopsys Inc. and the Effective Current Source Model backed by Cadence and Magma. It claims to improve run-times by a factor of 10 compared with existing tools. McCanny said that Altos wants to become a "trusted source" of characterization for regular static timing analysis libraries, thus building credibility for its statistical library characterization.
Statistical support comes with the Variety product, slated for release in the third quarter. It's essentially a superset of Liberate that will add the impact of process parameter variation and generate statistical libraries that account for both random and systematic variation.
The most commonly monitored parameters for statistical timing, McCanny observed, are voltage threshold, gate-oxide thickness and transistor length and width.
This information must come from foundries, and is considered to be proprietary. Consequently, Altos is initially targeting integrated device manufacturers. Many IDMs have their own in-house characterization tools, but statistical timing offers Altos an opportunity to replace some of those tools, McCanny said. Otherwise, he said, "they are going to have to invest a lot of people to build the statistical versions of their libraries."
One problem Altos faces is the lack of a standardized format for statistical timing models. Each statistical timer has its own format, which is why Altos must work individually with Extreme DA to support that company's timing analyzer. "We are also planning to generate other formats for other vendors, but we hope there will be a standard in this area," McCanny said. He noted that the Open Modeling Coalition (OMC), hosted by the Silicon Integration Initiative, has a working group that's developing a standard way of representing statistical models.
John Beatty, OMC chairman and senior technical staff member at IBM EDA, said that the OMC's statistical timing working group is working toward a standard that's targeted to be "internally complete" by the end of 2006. "At this point, there's no standard way to exchange information between a library and a [statistical timing] application," Beatty said. But it's not just a question of format, he noted--part of the challenge is to determine what information needs to be transferred in the first place.
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