In systematic variation, the process varies in the same direction by the same magnitude for every transistor within a small region, for example, within a logic cell. A classic example is the variation in channel length due to focus variation. The library modeling for systematic variation is similar to that of an 'intermediate' process corner.
Similar to global variation, each delay, transition, setup/hold, and pin capacitance table entry needs to be characterized for each systematic parameter, and represented in the library either as additional tables or sensitivities. The increase in characterization effort depends directly on the number of systematic parameters being modeled.
Finally, random variation models the process variations that apply to each transistor independently. Even for neighboring transistors inside the same cell, the variation may be different in direction and magnitude. In the analog world, this phenomenon is known as 'mismatch'. The magnitude of random variation is inversely proportional to the square root of the transistor area according to a relationship known as the Pelgrom's formula.
Therefore, cell characterization must make the appropriate parameter adjustment that is unique to each transistor before performing Spice simulation. As device geometries reduce, small imperfections in chip manufacturing result in increasing impact of these random variations. At 90nm, random variation accounts for up to 45% of the total process variation, and is projected to increase as scaling continues.
These process parameter variations pose new and significant challenges to cell characterization, where the characterization inputs are no longer consisting of fixed values. Consequently, the characterization outputs are standard deviations of the total impact due to these variations over each and every transistor inside a cell. Needless to say, a huge number of simulations are required to generate the standard deviation for each of the millions of table entries inside a modern cell library.
Circuit analysis drives statistical characterization
Figure 2 shows a simple buffer circuit with random threshold voltage variations to illustrate the characterization of delay and pin capacitance standard deviations. The variation in threshold voltage for each of the four transistors is represented by Vthn1, Vthn2, Vthp1 and Vthp2. Table 1 shows simulation results of the rising delay and pin capacitance variations due to each of these parameter variations.
In this example, the delay variation with a small output load is dominated by the first stage NMOS variation, whereas for a larger output load, the last stage PMOS variation has an increased delay impact. For pin capacitance, however, the first stage transistors have the most influence on the total variation. As one can see, the variation of each library value has its own unique composition of the aggregate impact from each transistor's variation on the data that is being characterized.
Figure 2 Simple buffer with random threshold voltage variations
Table 1 Random threshold voltage variation for a buffer and its effect on delay and pin capacitance
For each input slew, output load, and switching state combinations, the variation due to each transistor must be simulated, and the results combined to model the total variation impact due to all transistors inside the cell. This assumes the total impact due to all transistor variations can be approximated by the sum of the impact due to each transistor variation. The accuracy of this assumption is shown in Figure 3.
Even with this simplifying assumption, the amount of computation required for the characterization of random variation is increased by a multiple of (M*P) over a regular timing library, where M is the number of transistors inside a cell, and P is the number of random process parameters being modeled. For example, a simple 24 transistor D flip-flop with four random variation parameters (such as Vth and L for PMOS and NMOS) requires almost 100-fold increase in characterization time.
Furthermore, certain parameter variations are becoming more non-linear, requiring even more simulations to model variation effects accurately. This is clearly impractical and represents a major hurdle in the adoption of statistical static timing analysis and statistical timing driven optimization. New characterization methods are needed to overcome this barrier.