SANTA CRUZ, Calif. Promising a ten-fold speedup in cell library characterization for nanometer ICs, startup Altos Design Automation Inc. this week is introducing itself and its first product, Liberate. It's a step towards Altos' long-term goal of generating statistical timing models.
Altos was launched in January 2005 by Ken Tseng, CTO, and Kevin Chou, vice president of research and development. Both worked for CadMOS Design Technology Inc., a provider of noise analysis software, before its acquisition by Cadence Design Systems in 2001. At Cadence, the pair became key developers for Cadence's popular CeltIC crosstalk analysis tool.
Jim McCanny, Altos CEO, is also a CadMOS alumni, and he joined Altos in July 2005. He and the Altos founders felt there was "gaping hole" in the market, McCanny said. "Existing tools struggled to get the libraries that people wanted at 90 nm," he said. "A lot of them are just Perl scripts that run Spice."
The problem, McCanny said, is that the libraries needed at 90 nm and below have a lot more "views." They use cells with multiple threshold voltages and dynamic voltage scaling, and even for nominal static timing analysis, designers must look at different voltage and temperature corners for these cells.
Add in the process variations needed to support statistical analysis, and it may take 20 to 100 times longer to build a library, McCanny said. Altos promises to introduce a new generation of super-fast tools that will let designers characterize statistical libraries in about the same amount of time they currently spend characterizing nominal libraries.
For now, however, Altos is shipping Liberate, an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers. Liberate takes in a Spice netlist and Spice subcircuits, and automatically generates a characterized cell library. It supports both Composite Current Source (CCS) model backed by Synopsys and the Effective Current Source Model (ECSM) backed by Cadence Design Systems and Magma Design Automation.
Altos' claim to a ten-fold speedup is based on what the company calls an "inside view" approach. In brief, Liberate can look inside the cell to see how transistors are connected, and how the cell functions. The tool then eliminates redundant vector sequences that are electrically equivalent, thus reducing the amount of simulation needed. Further, Liberate includes an integrated Spice simulator, so there's no need to call an external tool although users have the option to use a third-party Spice simulator if they prefer.
Altos will support statistical timing models with its Variety product, slated for release in the third quarter. It's essentially a superset of Liberate that will add the impact of process parameter variations, and generate statistical libraries that account for both random and systematic variations.
Liberate is available now, starting at $95,000 for the one-year license. Further information about Altos and its plans for statistical modeling is available in an article in the print edition of this week's EE Times.
Authors from Altos and Extreme DA discuss characterization for statistical timing analysis in an EEdesign exclusive feature.
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