What's hot at DAC
Here's a sampling of recent announcements, presented in alphabetical order, that will take the spotlight at the Design Automation Conference.
Altos Design Automation Inc.
What to see: Fast IC library characterization, including generation of libraries for statistical timing analysis
Cadence Design Systems Inc.
What to see: Integrated solution for system-in-package RF design, space-based top-level router for analog/mixed-signal design
What to see: Compiler that can generate synthesizable RTL and cycle-accurate C from untimed C-language descriptions, allowing verification in native C environment
Javelin Design Automation Inc.
What to see: "System physical prototyping" tools that give designers physical information early in the IC design process
Liga Systems Inc.
What to see: NitroSim, a "hybrid simulator," based on a plug-in PCI card, that boosts RTL simulation 10 to 100 times
What to see: ModLyng, a graphical tool that generates behavioral or detailed analog/mixed-signal models in Verilog-AMS, VHDL-AMS or Mast
Magma Design Automation Inc.
What to see: New design-for-manufacturability (DFM) flow, including yield management and prediction, variability-aware characterization and lithography simulation
Mentor Graphics Corp.
What to see: Calibre nmDRC, a next-generation IC physical- verification tool that claims fast run-times, dynamic debugging and DFM capabilities
Sierra Design Automation Inc.
What to see: Olympus-SoC, a netlist-to-GDSII implementation suite including a new, "lithography aware" detailed router
What to see: NanoTime, a new transistor-level timing analysis tool with signal integrity; new IC Compiler release