LONDON The Power Forward Initiative (PFI), an industry group formed earlier this year to address obstacles to low-power IC design, is planning to attract more EDA companies into the project. The group will outline the initiative's roadmap at a special event at next week's Design Automation Conference in San Francisco.
EDA companies who join will be given access to Draft Version 1.0 of the Common Power Format (CPF) specification and be able to work with other Initiative members to evolve Version 1.0 towards broad industry adoption and standardization. Draft Version 1.0 is targeted for release by January 31, 2007 to PFI members.
The initiative is being driven by Cadence Design Systems, and companies already signed up include ARM Ltd, Royal Philips Electronics, TSMC, Applied Materials, AMD, Freescale Semiconductor, NEC and Fujitsu.
The group says getting more EDA companies on board is a key step in developing as quickly as possible the CPF specification, and submit this to a standards body for adoption.
"This is an important step in promoting the wide adoption of the Common Power Format specification," said Greg Buchner, vice president of engineering at ATI Research, and Power Forward Initiative advisory member.
Commenting on the formation of the initiative earlier this year, Mike Fister, president and CEO of Cadence said: "By uniting industry leaders, the Power Forward Initiative will steer the industry toward a broader, more systematic, and much more integrated approach to low-power design, providing a platform to enable higher-level exploration while leveraging the good building-block work we've all already done."
The CPF aims to link design, verification and implementation to reduce risk and increase predictability in chip power reduction. Members will work to adopt an automated design infrastructure aimed at reducing chip power consumption.
The group says the specification language will address the limitation in the design automation tool flow by capturing the designer's intent for power management. The CPF enables all design and technology related power constraints to be captured in a single file and applies that file across the design flow, providing a consistent reference point for design development and production.