RDRs are just another element in the "bag of tricks" for dealing with manufacturability issues, said Wally Rhines, Mentor Graphics CEO. "There will be more DFM in every [process] generation, independently of what happens with other design approaches," Rhines said.
From scorn to acceptance
The future did not always look so bright for RDRs and related methodologies that emphasize regular structures. According to early researchers in this area, chip makers originally turned up their noses at RDRs, quickly dismissing the technology because of a perceived need to sacrifice area and performance.
Robert Brayton, a processor of electrical engineering and computer sciences at the University of California, Berkeley, co-authored a book on structured regular silicon with former student Fan Mo (now with Synplicity Inc.). Brayton said chip makers initially showed no interest in his research during the late 1990s and early part of this decade. "They weren't willing to give up the area and delay," he said.
Larry Pileggi, Tanoto professor of electrical and computer engineering at Carnegie Mellon University (Pittsburgh) and director of the school's Center for Silicon System Implementation, has been conducting research on chip design using regular features since 1997 as part of a project for the university-based Microelectronics Advanced Research Corp. Back then, Pileggi said, some of the research group's member companies were perplexed about the point of the research.
But times have changed. Pileggi said he and his team have done research that proves the concept of regular design features at 65 nm with no area or performance penalty by changing the way synthesis is done and the way logic circuits are configured.
Everybody was thinking that if you 'go regular,' you have to pay a penalty," Pileggi said. "Nobody wants to pay that penalty until you have to. That's what we've shown--that you can do it without paying that penalty."
Papers on the benefits and trade-offs of RDRs have been presented at conferences in recent years. IBM researchers, for example, described RDR work in a paper given at the International Conference on Computer-Aided Design (ICCAD) in 2004. The paper described a project called LG3O (Layout using Gridded Glyph Geometry Objects).
The restrictions proposed in the paper included requiring that gate-forming polysilicon features have the same orientation and width, and that they be placed at a fixed pitch.
IBM's approach is to extend those restrictions on polysilicon features to all layers of a design, then tailor the layout flow and tools to take advantage of the restrictions.
IBM's experiments with 65-nm designs showed that LG3O does not impose much more restriction than the technology requirements themselves, according to the authors.
Farrar noted that IBM is evaluating the LG30 methodology now in an internal product design.
Indeed, he said, IBM already has restrictions on gate pitch and orientation at the 65-nm process node. While the goal is to achieve more-regular designs, he noted, "RDRs do not necessarily lead to gate array- or PLA-like design."
Possible RDR candidates: 1) bent gate 'on' as baseline,
2) poly-to-poly spacing, poly-to-diffusion spacing,
4) poly line end extension
and 5) bent gate line width.
Kahng co-authored a technical paper on RDR trade-offs that was presented at the Design Automation Conference in 2004. The paper was part of a Semi- conductor Research Corp. project that was jointly conducted UCSD and the University of Michigan, with collaboration from Luigi Capodieci, principal member of the technical staff Advanced Micro Devices Inc.
The research had focused on four RDRs, Kahng said. One was avoidance of bent gates, which is generally prohibited anyway these days. The others involved design rules for poly-to-poly minimum spacing, line-end extension and poly-to-diffusion minimum spacing.
The paper found that small increases in the minimum allowable polysilicon line-end extension can provide high levels of immunity to lithographic defocus conditions. The authors had also found that modifying the minimum field polysilicon-to-diffusion spacing could provide better manufacturability.
The authors demonstrated data volume reductions of 20 to 30 percent relative to a baseline "flexible" rule set, and reductions of nearly 50 percent in worst-case edge placement errors, from that set of basic RDRs. They reported that the penalty was only 0 to 5 percent in area and "a few percent in delay at most."
Others agree the penalties aren't large. "The expected drawback is that devices will be larger and there will be a performance hit," said Gartner's Smith. "But chip makers can't run these chips as fast as they want to, anyway, because of heat dissipation."
Cadence's Vucurevich said there probably won't be an area or performance penalty, so long as the restricted design rules apply to the device layers.
"If you start talking about RDR patterns for interconnect, all bets are off," the Cadence CTO said.
"Anytime you try to take away freedom from the designers, they are going to rebel," said Pileggi of Carnegie Mellon. "But I don't think that it's really true that moving to regular features stifles creativity.
"The design freedom is moving to a different level, and designers will need to find different ways to be creative."