San Francisco -- The effects of process variations loomed large at last week's Design Automation Conference here, as leading-edge chip designers spelled out the challenges they face at 65 nanometers and beyond. But many offered differing views and approaches for dealing with the problem.
One quandary facing chip makers is whether to try to model everything using design-for-manufacturability (DFM) tools, or to employ restricted design rules (RDRs) that will result in more regular fabrics. Discussions last week showed that designers are hoping for a balanced approach that involves some restrictions, but leaves enough area and performance on the table so there's still some point in going to lower process nodes.
Another issue that's unresolved is whether and when to use statistical timing analysis. Some designers are clearly skeptical, believing that it's effective for random variations only. In any case, there seems to be support for separating out systematic variations and modeling those before going to a statistical approach.
But one thing is clear: users who have delved into 65 nm are feeling the pain. "My biggest concern at the 65-, 45- and 32-nm process nodes is variability," said Ho-Kyu Kang, vice president at Samsung Electronics. "Critical design rules have been scaled by 30 percent every other year, but variability has not scaled by the same rule. So variability becomes bigger and bigger as design rules scale."
STMicroelectronics foresees a "discontinuity" with respect to the design tool solutions needed at 45 nm and beyond, said Philippe Magarshack, vice president of central CAD at STMicroelectronics. "We're dealing with restricted design rules on the one hand, and on the other looking for any way we can to predict system variability and account for it in design, rather than with design margins."
Clive Bittlestone, fellow and physical verification manager at Texas Instruments Inc., noted that simple corner analysis with margins is becoming a struggle. "That keeps me awake at night," he said. "It's a key shift." Most design-for-manufacturing effects are served by available tools, but "true" variability analysis and optimization is still needed, he said.
What's most bothersome? Bittlestone showed a list of design concerns at various process nodes. His top concerns at 65 nm are gate shape, design rule checking, models, statistical timing analysis and placement and routing. Critical-area analysis, stress and extraction ranked lower.
Aggressive users often feel shortchanged by commercial EDA vendors. But Magarshack said users can't expect tools too soon. "Until we do designs at these nodes, we can't prioritize the issues and ask for solutions," he said. "There are no tools for 45 nm for us to use--that's obvious. So it's crucial to have good working relationships with the right partners."