Orlando, Fla. -- In an industry obsessed with miniaturization, Freescale Semicon- ductor Inc. has high hopes for a packaging technology that could radically alter the way chip sets are deployed.
A proprietary technique called redistributed chip packaging (RCP) delivers about a 30 percent reduction in packaged-die area and thickness, said executives at the Freescale Technology Forum here last week.
Using photolithography and copper-plating steps to create chip-to-chip interconnects, RCP eventually will replace traditional wire bond, ball grid array and flip-chip packages, said Freescale chief executive Michel Mayer. Full-scale manufacturing is expected in 2008, Mayer said. At that time, Freescale expects to produce 200 million to 300 million RCP chips using internal manufacturing lines for PowerQuicc, DSP, baseband processor and power amplifier products.
Freescale plans to license the technology to packaging companies and other semiconductor vendors, making it an in- dustrywide standard, Mayer said. "We believe that RCP will have the right cost structure to make it a big deal right out of the gate." It could be used with system-in-package (SiP) and package-on-package technologies, plus modules with integrated cavities, he said.
Sumit Sadana, Freescale's chief strategy officer, called RCP "a true breakthrough--we end up with a package that is only a little bit bigger than the die itself, and you don't need to deal with wire bonding or [flip chip's] C4 bumps." The approach cuts costs "without compromising on performance," he said.
In multichip modules used during the past two or three decades, chips were mounted on expensive low-temperature-coefficient ceramic substrates. "With LTCC, we mounted the die on the substrate. With RCP, we place the die in a panel and build interconnect around it," said Karl Johnson, a director at Freescale's lab in Tempe, Ariz., where the technology was developed over the past three years under team leader Beth Keser. "That introduces the simplicity and elegance of proven semiconductor process techniques. And it eliminates the cause of defects, which come from stresses between the solder balls in flip-chip packages when they are attached to different substrate materials."
At the forum's technology lab, Freescale engineer Tran Phu demonstrated a side-by-side comparison of working GSM/Edge cell phone chip sets--one in the traditional plastic ball grid array (BGA) packaging and the other in RCP. Using RCP, the entire GSM module--combining power management, RF, baseband and power amplifier chips--measured 2.5 x 2.5 cm, about a quarter of the size of today's commercial GSM/Edge modules. Phu said additional optimization can reduce the RCP implementation by 20 percent more.
Freescale also demonstrated long-term-evolution OFDM devices for 3G phones, with one chip in a traditional BGA package measuring 13 mm2 and another in RCP measuring 9 mm2. Sadana, a former IBM design engineer who is also Freescale's acting chief technology officer, said that RCP gives Freescale a means of combining, for example, an optimized radio frequency die, built using a silicon germanium process, with a digital IC for baseband and applications processing. By using optimized process technologies and then combining dice in an RCP module, Sadana said, Freescale could offer higher handset performance than its rivals.
Dozens of configurations
The RCP approach begins by separating each die within an IC and placing the individual dice into a grid configuration in a panel the size of a 200-mm wafer, said Johnson. Dozens of combinations of the four GSM/Edge chips, for example, could be arranged on the panel and attached with adhesives. Epoxy and molding compound are applied to the die, connection patterns are lithographically defined, vias are etched through a dielectric to the chip's I/O pad contacts and copper interconnects are electroplated. Because all of the chips in a module are packaged together, the approach eliminates wire bonding, as well as solder reflow techniques and flip-chip C4 solder bumps.
These photolithography, etch and plating steps result in one or two interconnect levels on both the top and bottom layers of a die, connecting the dice on the top side and providing links to the system substrate on the bottom. The copper interconnects on the top side of the die provide chip-to-chip connections. On the bottom side, RCP techniques are used to define either land grid arrays or C5 balls to link the die to the substrate of a cell phone handset, for example.