SAN FRANCISCO Top-tier EDA vendor Mentor Graphics Corp. said Monday (Aug. 14) it has reached an agreement to supply "select EDA technologies" for design-for-manufacturability (DFM) and design-for-test (DFT) to Freescale Semiconductor Inc.
The deal is significant because Freescale (Austin, Texas) made waves last November when it designated EDA market leader Cadence Design Systems Inc. as its primary EDA vendor. Freescale and Cadence both stressed at the time that the deal does not tie Freescale to buying Cadence tools exclusively, but that the bulk of the company's design work would be done with Cadence tools.
Mentor (Wilsonville, Ore.) said it plans to provide Freescale with EDA tools in several focused areas of the nanometer chip design flow, including the areas of DFT, physical verification and analysis, resolution enhancement technologies (RET) and post-tapeout DFM. The new arrangement expands on an existing collaboration, Mentor said. Financial terms of the deal were not disclosed.
"In the emerging area of DFM, Freescale continues to invest significantly in order to provide DFM capability at every phase of the chip design process from architecture phase to mask preparation phase," said Ross Hirschi, Freescale's director of methodologies and flow development. "This helps to ensure that our chips are manufacturable by design. Mentor's solutions fit well in specific areas of Freescale's comprehensive DFM flow."