SAN FRANCISCO The increase in IC design cost and the size of design teams at the 65-nanometer node presents an opportunity for EDA, which can increase its growth rate if it can provide more productive solutions that enable customers to do 65-nm designs without the need to continually increase headcount, according to Handel Jones, CEO of International Business Strategies Inc.
"What the EDA industry has to do is look at headcounts of design teams, then look at how you slow down the increase in headcount or reduce headcount through providing more productive tools," Jones said.
Jones believes the EDA market is poised to outgrow the IC industry. In 1996, he said, R&D expenditures for semiconductor companies were roughly 5.5 percent of revenues. By 2010, he said, product R&D will be almost 14 percent of revenue, with some companies spending as much as 20 to 25 percent.
"Companies can't keep increasing R&D," Jones said. "They have got to make engineers more productive. The way you do that is increasing the tool productivity."
Jones believes that 65-nm wafer volumes are going to be ramping a lot faster than originally thought, with chip makers employing techniques like voltage islands and back biasing to manage leakage current. Companies have shown willingness to make "significant compromises" to achieve higher gate density at 65-nm, including compromises in chip area and performance, as well as migration to multicore architectures, Jones said.
Jones sees leakage current emerging as the top problem facing chip designers at 65-nm. His beliefs are consistent with a recent EE Times survey, which found that chip designers are currently most concerned about functional verification and timing closure, but that, as feature sizes shrink, they expect that managing leakage current will become their biggest concern.
"We think a complete new series of tools and environments will emerge [to address this area]," Jones said. "This is a whole new set of variableshow you do tradeoff current and frequency? How you do those tradeoffs is something that should be done at very beginning, not at the back end. This is a complete change."
One of the companies focused on this area is Zenasis Technologies (San Jose, Calif.). Zenasis employs a patented "hybrid optimization" technology to analyze designs at the logic, physical and transistor levels.
According to Dennis Harmon, Zenasis president and CEO, companies are grappling with tradeoff decisions to alleviate the leakage current problem at 65-nm and even at higher nodes.
"But you don't improve leakage power at the expense of frequency," Harmon said. "I would say, no matter what design node you are at, you are worried about operating frequency. Nobody wants things to run slow. People will always want things to run faster."