SAN FRANCISCO Organizers of the 2007 Design and Verification Conference (DVCon) have issued a call for paper, panel and tutorial submissions.
Proposals that reflect real experiences using hardware design and verification languages, advanced tools and methodologies are encouraged, DVCon organizers said through a statement Tuesday (Aug. 29). All submissions related to using HDLs, HVLs or other languages used for hardware design or verification will be considered, according to the statement.
Panel and paper proposals are due Sept. 19. Further details about the topics can be found on DVCon's Web site.
Proposals are also being accepted for special sessions and sponsored tutorials, according to the statement.
Special sessions may consist of embedded tutorials of one to two hours in length or may be focused on a specific topic with a list of invited papers/presentations relevant to that topic, the organizers said. Sponsored tutorials are due Oct. 5.
DVCon 2007, sponsored by EDA standards organization Accellera, is scheduled for Feb. 21-23 at the Double Tree Hotel in San Jose, Calif. The conference will focus on the use of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e, and Vera, as well as general purpose languages such as C and C++, according to the organizers.