SAN JOSE, Calif. Cadence Design Systems executives set forth technology roadmaps for the company's key product lines at the CDNLive! conference here Tuesday (Sept. 12), and identified a new project, Torino, as a next-generation digital IC initiative. To build its technology strategy, Cadence is relying on increasingly integrated "platforms."
At his CDNLive! keynote speech, Mike Fister, Cadence CEO, said that Cadence is increasingly taking a "multidisciplinary approach" to its product offerings. The Virtuoso platform, for instance, addresses analog, custom digital, RF and memory design, along with process development, he said. Further, Fister said, it unites architectural design, simulation, optimization, and yield-aware layout.
"In EDA, since we're functional experts, we often attack pieces of the design continuum," Fister said. "What we want to do is move up to system design." In this context, Fister briefly mentioned Torino, a name that appeared in a recent quarterly earnings review, as a new project that will help give designers better results up front by linking specifications to the RTL-to-GDSII design flow.
Eric Filseth, corporate vice president of product marketing at Cadence, said Torino is the company's "next generation digital implementation initiative." He said that technology from the Torino project will be integrated into the SoC Encounter digital IC design platform starting in the fourth quarter of 2006 and continuing into 2007.
Torino, said Filseth, is aimed at next-generation consumer IC designs. It will take advantage of the fact that in these designs, much of the chip is reused. This, he said, makes it possible to support "specification-driven design starting at the requirements phase."
"We think the next generation flow needs to start implementation at the specification stage," Filseth said. "The work you do between the specification and RTL has a huge impact on power, area and performance." Thus, he said, Torino will "automate a lot of stuff up front that people do manually today."
Torino will also address design for manufacturability, and will address the "substantial need to increase the capacity of the whole flow," Filseth said. He noted that Torino is not a separate entity like Cadence's Catena organization, but is a project within Cadence's digital IC product group. Filseth declined to provide further details about products that will emerge from Torino.
At a CDNLive! press conference, executives presented a 2007-2008 technology roadmap for Cadence's four primary technology platforms Virtuoso, Encounter, the Incisive verification platform, and the Allegro pc-board solution. Moshe Gavrielov, executive vice president of Cadence's verification division, said Incisive improvements will focus on verification management and system-level quality.
The 2007-2008 Incisive roadmap includes planning and management for RTL timing and power closure, hardware/software coverage and metrics, "advanced formal" verification, improvements in bug and coverage closure, system-level SystemVerilog, "e" language extensions for analog/mixed-signal, and new verification intellectual property.
Cadence's Power Forward initiative will play a key role in the Encounter roadmap, said Jim Miller, executive vice president at Cadence. "We have to have a holistic approach to today's low-power implementation, which typically comes from a grab bag of techniques," he said. "Power Forward lets customers connect power tools in the same way that RTL and GDSII are connected."
The 2007-2008 Encounter roadmap includes multi-supply voltage prototyping, variation-aware power optimization, statistical and thermal analysis, multi-threaded implementation, early virtual prototyping, variation-aware placement and routing, 45 nm and 32 nm rules and requirements, variation analysis, and unified constraint management.
The Virtuoso roadmap includes RF design enhancements, routing enhancements for 65 nm and 45 nm designs, enhanced circuit simulation engines, design awareness of manufacturing and yield, and multi-objective optimization.
The Allegro roadmap includes power and signal integrity, support for 10 Ghz and faster designs, databus-aware design and routing, higher-level constraints, and system design through table-driven techniques.
Cadence also plans to enhance its existing analog/mixed-signal and RF design methodology kits, and to roll out new kits for low power design, functional verification for wireless, and functional verification for PCI Express. Cadence kits include reference designs and documentation along with tools.
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