SAN FRANCISCO Total power, leakage power, electromigration and dynamic voltage drop are the biggest concerns for today's system-on-chip (SoC) designers, according to the results of a survey by power-focused EDA vendor Sequence Design Inc.
Twenty-five percent of respondents flagged each parameter as the most critical in design closure and signoff, Sequence (Santa Clara, Calif.) said. The survey results are based on 115 responses collected during the Design Automation Conference (DAC) in July, Sequence said.
The results track closely with the "EE Times 2006 EDA Users Survey," which found that chip designers are most concerned about functional verification and timing closure, but that as feature sizes shrink, they expect that managing leakage current will become their biggest concern.
According to the designers surveyed, the highest growth rate of designs is at the 65-nanometer node, with nearly 90 respondents saying that they were either working at 65-nm or moving to the node. The majority of designs, the survey noted, are still thriving at 90-nm.
Thirty-eight percent of respondents stated that they were concerned about achieving power specifications for their SoC designs. Other often-stated concerns included battery life (26 percent) IC packaging costs (15 percent) reliability (12 percent) and yield (9 percent.)
The most often cited techniques to manage power were clock gating (24 percent); multi-voltage-threshold libraries (22 percent); power gating (15 percent); voltage islands (13 percent); and clock power optimization (13 percent). Respondents were allowed to specify more than one technique.
More than 50 percent of respondents indicated that they manage power through both front-end design and back-end implementation efforts, according to Sequence.
Regarding design elements, besides datapath and memory, about half of the designers canvassed used MPU/DSP cores and 44 percent designed/used analog blocks, Sequence said.
Verilog was cited as the language of choice by almost 50 percent of respondents, followed by System Verilog with 20 percent and VHDL with 9 percent. For higher level design, 16 percent reported designing in System C or C++; while commercial ESL tools were currently used by only 5 percent of respondents, Sequence said.
General comments from designers favored power management tools across the board, especially for RTL power analysis and other areas, Sequence said.
The survey results are based on 115 responses. The industry sectors most represented among survey respondents are wireless telecommunications (31 percent), computer networking (27 percent.) and portable electronics equipment (21 percent), according to Sequence.