Santa Clara, Calif. -- Giving structure to an emerging IC power standards effort, the Accellera standards organization last week launched the Unified Power Format (UPF) technical subcommittee, amid offers of technology donations from Synopsys, Mentor Graphics, Magma Design Automation and Sun Microsystems.
It's a promising start for a new standard that will allow users to describe low-power design intent in multivendor tool flows. But with Cadence Design Systems and its allies still targeting the IEEE for the Power Forward Initiative (PFI), the industry remains divided over power standards.
At the UPF kickoff meeting Sept. 13, it became clear that Cadence's Common Power Format (CPF) isn't the only technology aimed at low-power specifications. Synopsys, Mentor and Magma all have their own approaches for specifying power intent, and they seem willing to donate technology to Accellera on an equal basis. Accellera would gladly accept a donation of CPF, too--just as Cadence has invited its leading competitors to join the PFI advisory group or the forthcoming IEEE working group.
The formation of the UPF working group follows a meeting at the July Design Automation Conference organized by Texas Instruments and Nokia. Along with Synopsys, Mentor and Magma, they felt PFI was not sufficiently "open, inclusive and fast" (see Aug. 7, page 1). Cadence has since invited its EDA competitors to join and has speeded up the original PFI timetable by more than a year.
Today, a key difference remains. Cadence believes CPF is past the Accellera development phase and is ready to go directly to the IEEE for standardization. The 14-member PFI advisory board recently submitted an IEEE project authorization request (see Sept. 4, page 12). Companies behind UPF want a standard that results from contributions from multiple vendors, and they note that CPF is still owned by Cadence.
"UPF doesn't even exist," said Jan Willis, senior vice president of industry alliances at Cadence, the day before the kickoff meeting. "Who's contributing? Is it usable?" The new effort, she said, can expect to take at least 10 months to develop after seed contributions are made--a process that Cadence has already gone through with CPF.
But the UPF technical subcommittee has outlined an aggressive schedule--a design objectives document by this week, a first draft for review by Oct. 30, a draft for Accellera review by Nov. 30 and a handoff to the IEEE or other standards body by Jan. 31. The window for donations will be open past an Oct. 5 meeting called by Accellera and the Silicon Integration Initiative (Si2) to get user input on power standards.
"The timeline is aggressive, but we believe there's existing technology that can be leveraged to get us there," said Stephen Bailey, UPF technical subcommittee chair and product-marketing manager for functional verification at Mentor Graphics. He noted that the leading EDA vendors already have their own power formats, and that what needs to be done now is mostly a matter of coming up with a common syntax.
An Accellera effort with multiple technology donations might have been ap- propriate a year ago before CPF was developed, Willis said, but going back to such a process now would slow everything down. "These are the tactics of competitors who want to slow something down or kill it," she said.
On the other hand, UPF backers insist that Cadence is trying to shove CPF through too quickly. The proposed CPF IEEE working group, Bailey said, "is basically a rubber stamp of CPF, and CPF development is not open."
Overcoming the hodgepodge
What may be lost in the vendor infighting is why this effort is important in the first place. "Power has become the dominant factor in the design of today's electronic systems," said Bailey. "But the current state is a hodgepodge of commercial ad hoc solutions." Today, he noted, users are forced to specify power intent multiple times, in different ways for different tools.
At the system level, Bailey noted, designers need to experiment with power islands and voltage domains, budget dynamic power and estimate power usage. For example, he said, they need a way to specify which information in an intellectual property (IP) block needs to be saved when power is turned off.
At the register-transfer level, users need a way to specify power islands, voltage thresholds, isolation and retention. They need constraints and specifications that can drive functional verification, synthesis and power analysis. Bailey said the UPF standard will help ensure the portability of power information across different vendors' tools, allow IP reusability, and support library modeling, characterization and verification.
Bailey presented a detailed technology proposal from Mentor Graphics for specifying power intent. It uses an ASCII "side file" to capture intent, along with a set of corresponding modeling guidelines. The side file is language-neutral, he said, and doesn't require users to alter RTL source code.
Called the power configuration file (PCF), it captures information about voltage domains, power islands, the power control network and power-aware functionality such as retention. Modeling guidelines specify how features like retention behave.
Jim Sproch, senior director of R&D at Synopsys, said his company's proposed donation covers two areas--extensions to existing languages to define power characteristics and specifications for the representation of signal-switching activity. He showed three proposed SystemVerilog constructs--Power, which defines RTL power domains; Isolate, which models isolation cells; and Retain, which models retention registers.
Sproch also announced that Synopsys' Switching Activity Interchange Format (SAIF), currently open-source, will be donated to Accellera.
Yatin Trivedi, director of product marketing at Magma, listed a number of requirements for a low-power standard. He noted that RTL pragmas are needed for such tasks as clock gating, multiple voltage thresholds, voltage domains, retention flip-flops and level shifters. He also said there's a need for power constraints for design for test and packaging. Magma will donate "to the extent we have something to contribute," he said.
Sun Microsystems will donate ASCII text files that it uses internally for power behavior, said Rob Mains, senior distinguished engineer at Sun.
System-level design should be a crucial part of a power standards effort, said Graham Hellestrand, founder of Vast Systems. "Power modeling at the systems level will determine the specification of the silicon portion of a product, and must be integrated into system and silicon design flows," he said. "I can't possibly see how this can be done in a one-month exercise."
Meeting participants agreed that moving to the systems level is important, but noted that the initial UPF standards will focus on the RTL and gate levels.
Victor Berman, group director of industry alliances at Cadence, sat through all the UPF presentations, but he said later that CPF is still far ahead because it "unifies information in one place that goes through the entire flow." But Berman did not rule out a possible contribution of CPF to Accellera. "No doors have been closed," Berman said.
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