SAN FRANCISCO Electronic system level EDA vendor Tenison Design Automation Monday (Sept. 25) announced IP Exchangea tool provided for intellectual property (IP) vendors, semiconductor and fabless companies to address the problem of safely delivering verification IP to external customers and internal teams.
According to Tenison (San Jose, Calif.), IP Exchange helps companies meet product delivery and time-to-market expectations by addressing the lack of available system-level and verification IP models.
"Tenison's IP Exchange not only removes key barriers for adoption of our customers' IP, we also believe it will change the way design teams use and evaluate IP, especially for SoC design teams who must assemble IP from multiple sources to make their products," said Martin Harding, Tenison CEO, in a statement.
Tension maintains that the IP Exchange tool provides both architectural and "what if" analysis, software evaluation of IP, platform hardware evolution and removes legal and contractual barriers to IP exchange.
According to Tenison, IP Exchange customers and partners use Tenison's VTOC product line to create C++ and SystemC models from RTL for distribution outside the customer's company or work group. Using tools provided through IP Exchange, the customer can dictate what level of visibility each C++ or SystemC model has for each customer and the terms for each model's license. IP Exchange allows IP designers to automatically generate C models from RTL and maintain control of the IP throughout the model's life cycle, the company claims.
IP Exchange is commercially available now. Pricing information was not provided.
Also Monday, Tenison announced that its VTOC products will be integrated into ARC's ARChitect Processor Configurator, enabling ARC customers to generate SystemC cycle accurate models of ARC's configurable processors and subsystems earlier in the SoC design process.