SAN FRANCISCO Intel Corp. plans to add more than 50 new streaming SIMD extensions (SSE4) to extend the Intel 64 instruction set architecture for the 45-nanometer node, according to Pat Gelsinger, senior vice president and general manager of the digital enterprise group.
Delivering a keynote address at on the second day of the Intel Developer Forum here Wednesday (Sept. 27), Gelsinger said the extensions would enable users to better take advantage of Intel's next-generation 45-nm manufacturing process and expand the performance and capabilities of Intel architecture. The company plans to start 45-nm in the second half of 2007.
Gelsinger announced the publication of a white paper describing the new SSE4 instructions and application targeted accelerators. The white paper is available via Intel's Web site.
Later, Gelsinger acknowledged that, by publishing the instructions, they would be subject to scrutiny by competitors, chiefly Advanced Micro Devices Inc.
"We needed to be more open to enable customers to benefit from these extensions," Gelsinger said. "As a consequence, competitors will be able to see them a lot sooner as well."
The white paper describes the SSE4 and application targeted accelerators as an important milestone. The company said it is continuing to work with a community of independent software vendors to deliver instruction set extensions that enhance the ability of their products to provide real benefit to customers.
The white paper calls the SSE4 extensions the company's most important set of extensions since the SSE2 extensions, unveiled in 2000.
New products based on the Intel 64 instruction set architecture will first appear next year for applications including graphics, video encoding and processing, 3-D imaging, gaming, web servers and application servers.
In an address that last more than 70 minutes and featured several guest appearances by executives from Intel customers and software vendors, Gelsinger also previewed Intel's forthcoming quad-core products for servers and workstations and highlighted new industry standards initiatives, including a new PCI Express technology, codenamed "Geneso," co-developed with IBM.
Gelsinger responded strongly to criticism Intel has received for making its initial quad-core devices multi-chip packages containing two dual-core chips, rather than a monolithic four-core processor.
"At 65-m, the [multi-chip package] approach is the right way to do it," Gelsinger said. "This is just the right way to deliver quad core at 65-nm, and we are not apologizing for it."
Gelsinger opened the address by boasting of Intel's execution over the past several months, saying the company introduced 40 new processors over the summer. He called 2006 "an amazing year."