SHANGHAI, China Samsung Electronics has developed a 50-nanometer, 1-gigabit DDR2 DRAM chip based on three-dimensional transistor design and multilayered dielectric technology.
Samsung said it used a selective epitaxial growth transistor (SEG Tr), which hastens the flow of electrons by creating a wider channel. The result is lower power consumption and higher performance, although Samsung did not offer details.
To improve signaling, the chip's designers used a multilevel dielectric layer (consisting of ZrO2/Al2O3/ZrO2) within the SEG transistor. The material also stores higher volumes of electrons, the company said, which will increase storage capacity. Samsung also applied its proprietary RCAT (Recess Channel Array Transistor) 3D transistor technology to the chip, which doubles the refresh rate of DRAM. Samsung claims this will be "a critical technology" in enabling the future scalability of DRAM.
DRAM is beginning to trail in the scaling race to its upstart cousin, NAND flash. Samsung unveiled a 32-Gbit chip made on 40-nm process technology in early September, just months after IM Flash Technologies LLC, a joint venture of Intel Corp. and Micron Technology Inc., started sampling a 4-Gbit NAND flash memory based on a 50-nm process.
For Samsung, the move to 50 nm boosts DRAM production by 55 percent over the 60 nm node, the company said. Mass production will begin in 2008. By 2011, Samsung said it will be the mainstream technology in a DRAM market it believes will hit $55 billion.